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author | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-23 22:40:42 +0000 |
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committer | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-23 22:40:42 +0000 |
commit | 0e2c2fe1d1eec5482078147d551215a58604cc3a (patch) | |
tree | 5b829774e1f67afc86acb0a0f968d0a6a4766246 /src/target | |
parent | 6319ea33f7369823043eaefdb72b7463e760be27 (diff) | |
download | openocd+libswd-0e2c2fe1d1eec5482078147d551215a58604cc3a.tar.gz openocd+libswd-0e2c2fe1d1eec5482078147d551215a58604cc3a.tar.bz2 openocd+libswd-0e2c2fe1d1eec5482078147d551215a58604cc3a.tar.xz openocd+libswd-0e2c2fe1d1eec5482078147d551215a58604cc3a.zip |
- Fixes '>>' whitespace
- Replace ')\(>>\)\(\w\)' with ') \1 \2'.
- Replace '\(\w\)\(>>\)(' with '\1 \2 ('.
- Replace '\(\w\)\(>>\)\(\w\)' with '\1 \2 \3'.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2369 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target')
-rw-r--r-- | src/target/arm_adi_v5.c | 6 | ||||
-rw-r--r-- | src/target/arm_disassembler.h | 2 | ||||
-rw-r--r-- | src/target/target.c | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index ea3b2792..146f89f4 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1103,12 +1103,12 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1); mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2); mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3); - component_start = component_base - 0x1000*(c_pid4>>4); + component_start = component_base - 0x1000*(c_pid4 >> 4); command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", pid4 0x%" PRIx32 ", start address 0x%" PRIx32 "",component_base,c_pid4,component_start); - command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */ + command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1 >> 4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */ command_print(cmd_ctx, "\t\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 ", CID0, 0x%" PRIx32 "",c_cid3,c_cid2,c_cid1,c_cid0); command_print(cmd_ctx, "\t\tPID3 0x%" PRIx32 ", PID2 0x%" PRIx32 ", PID1 0x%" PRIx32 ", PID0, 0x%" PRIx32 "",c_pid3,c_pid2,c_pid1,c_pid0); - /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */ + /* For CoreSight components, (c_cid1 >> 4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */ } else { diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index 7d914bfd..00c4b295 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -198,6 +198,6 @@ extern int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instructio extern int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction); extern int arm_access_size(arm_instruction_t *instruction); -#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28]) +#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28]) #endif /* ARM_DISASSEMBLER_H */ diff --git a/src/target/target.c b/src/target/target.c index b7685966..89d2c88a 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -2792,7 +2792,7 @@ static void writeLong(FILE *f, int l) int i; for (i=0; i<4; i++) { - char c=(l>>(i*8))&0xff; + char c=(l >> (i*8))&0xff; writeData(f, &c, 1); } @@ -2883,7 +2883,7 @@ static void writeGmon(uint32_t *samples, uint32_t sampleNum, char *filename) val=65535; } data[i*2]=val&0xff; - data[i*2+1]=(val>>8)&0xff; + data[i*2+1]=(val >> 8)&0xff; } free(buckets); writeData(f, data, length * 2); |