Remove whitespace at end of lines, step 1.

- Replace '\s*$' with ''.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2379 b42882b7-edfa-0310-969c-e2dbd0fdcd60

25 files changed, 630 insertions, 630 deletions

diff --git a/src/target/algorithm.h b/src/target/algorithm.h
index 316498b3..15e3cf22 100644
--- a/src/target/algorithm.h
+++ b/src/target/algorithm.h
@@ -35,7 +35,7 @@ typedef struct mem_param_s
 	uint32_t size;
 	uint8_t *value;
 	enum param_direction direction;
-} mem_param_t; 
+} mem_param_t;
 
 typedef struct reg_param_s
 {
diff --git a/src/target/arm11.c b/src/target/arm11.c
index b5edd8fc..57dcd2f8 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1888,7 +1888,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
 		if (values[i] > arm11_coproc_instruction_limits[i])
 		{
 			LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
-				  (long)(i + 2), 
+				  (long)(i + 2),
 				  arm11_coproc_instruction_limits[i],
 				read ? arm11_mrc_syntax : arm11_mcr_syntax);
 			return -1;
@@ -1913,10 +1913,10 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
 		arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
 
 		LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
-			 (int)(values[0]), 
-			 (int)(values[1]), 
-			 (int)(values[2]), 
-			 (int)(values[3]), 
+			 (int)(values[0]),
+			 (int)(values[1]),
+			 (int)(values[2]),
+			 (int)(values[3]),
 			 (int)(values[4]), result, result);
 	}
 	else
diff --git a/src/target/arm926ejs.h b/src/target/arm926ejs.h
index 6bb2a2e4..7adbf1fb 100644
--- a/src/target/arm926ejs.h
+++ b/src/target/arm926ejs.h
@@ -39,9 +39,9 @@ typedef struct arm926ejs_common_s
 } arm926ejs_common_t;
 
 extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap);
-extern int arm926ejs_register_commands(struct command_context_s *cmd_ctx); 
-extern int arm926ejs_arch_state(struct target_s *target); 
-extern int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); 
+extern int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
+extern int arm926ejs_arch_state(struct target_s *target);
+extern int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 extern int arm926ejs_soft_reset_halt(struct target_s *target);
 
 #endif /* ARM926EJS_H */
diff --git a/src/target/arm9tdmi.h b/src/target/arm9tdmi.h
index fc84e4bb..28be9b6c 100644
--- a/src/target/arm9tdmi.h
+++ b/src/target/arm9tdmi.h
@@ -59,7 +59,7 @@ extern int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
 
 extern int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed);
 extern int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in);
-extern int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be); 
+extern int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be);
 extern void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]);
 extern void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]);
 
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 01b7e0cb..19e48315 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -104,7 +104,7 @@ typedef struct swjdp_common_s
 
 } swjdp_common_t;
 
-/* Accessor function for currently selected DAP-AP number */ 
+/* Accessor function for currently selected DAP-AP number */
 static inline uint8_t dap_ap_get_select(swjdp_common_t *swjdp)
 {
 	return (uint8_t)(swjdp ->apsel >> 24);
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 9ba28657..94479261 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -33,9 +33,9 @@ char *arm_condition_strings[] =
 };
 
 /* make up for C's missing ROR */
-uint32_t ror(uint32_t value, int places) 
-{ 
-	return (value >> places) | (value << (32 - places)); 
+uint32_t ror(uint32_t value, int places)
+{
+	return (value >> places) | (value << (32 - places));
 }
 
 int evaluate_pld(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
@@ -44,9 +44,9 @@ int evaluate_pld(uint32_t opcode, uint32_t address, arm_instruction_t *instructi
 	if ((opcode & 0x0d70f0000) == 0x0550f000)
 	{
 		instruction->type = ARM_PLD;
-		
+
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD ...TODO...", address, opcode);
-		
+
 		return ERROR_OK;
 	}
 	else
@@ -54,7 +54,7 @@ int evaluate_pld(uint32_t opcode, uint32_t address, arm_instruction_t *instructi
 		instruction->type = ARM_UNDEFINED_INSTRUCTION;
 		return ERROR_OK;
 	}
-	
+
 	LOG_ERROR("should never reach this point");
 	return -1;
 }
@@ -62,9 +62,9 @@ int evaluate_pld(uint32_t opcode, uint32_t address, arm_instruction_t *instructi
 int evaluate_swi(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	instruction->type = ARM_SWI;
-	
+
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSWI 0x%6.6" PRIx32 "", address, opcode, (opcode & 0xffffff));
-	
+
 	return ERROR_OK;
 }
 
@@ -73,30 +73,30 @@ int evaluate_blx_imm(uint32_t opcode, uint32_t address, arm_instruction_t *instr
 	int offset;
 	uint32_t immediate;
 	uint32_t target_address;
-	
+
 	instruction->type = ARM_BLX;
 	immediate = opcode & 0x00ffffff;
-	
+
 	/* sign extend 24-bit immediate */
 	if (immediate & 0x00800000)
 		offset = 0xff000000 | immediate;
 	else
 		offset = immediate;
-	
+
 	/* shift two bits left */
 	offset <<= 2;
-	
+
 	/* odd/event halfword */
 	if (opcode & 0x01000000)
 		offset |= 0x2;
-	
+
 	target_address = address + 8 + offset;
-	
+
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32 "", address, opcode, target_address);
-	
+
 	instruction->info.b_bl_bx_blx.reg_operand = -1;
 	instruction->info.b_bl_bx_blx.target_address = target_address;
-	
+
 	return ERROR_OK;
 }
 
@@ -106,32 +106,32 @@ int evaluate_b_bl(uint32_t opcode, uint32_t address, arm_instruction_t *instruct
 	uint32_t immediate;
 	int offset;
 	uint32_t target_address;
-	
+
 	immediate = opcode & 0x00ffffff;
 	L = (opcode & 0x01000000) >> 24;
-	
+
 	/* sign extend 24-bit immediate */
 	if (immediate & 0x00800000)
 		offset = 0xff000000 | immediate;
 	else
 		offset = immediate;
-	
+
 	/* shift two bits left */
 	offset <<= 2;
-	
+
 	target_address = address + 8 + offset;
 
 	if (L)
 		instruction->type = ARM_BL;
 	else
 		instruction->type = ARM_B;
-	
+
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tB%s%s 0x%8.8" PRIx32 , address, opcode,
 			 (L) ? "L" : "", COND(opcode), target_address);
-	
+
 	instruction->info.b_bl_bx_blx.reg_operand = -1;
 	instruction->info.b_bl_bx_blx.target_address = target_address;
-	
+
 	return ERROR_OK;
 }
 
@@ -140,32 +140,32 @@ int evaluate_b_bl(uint32_t opcode, uint32_t address, arm_instruction_t *instruct
 int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	uint8_t cp_num = (opcode & 0xf00) >> 8;
-	
+
 	/* MCRR or MRRC */
 	if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c400000))
 	{
 		uint8_t cp_opcode, Rd, Rn, CRm;
 		char *mnemonic;
-		
+
 		cp_opcode = (opcode & 0xf0) >> 4;
 		Rd = (opcode & 0xf000) >> 12;
 		Rn = (opcode & 0xf0000) >> 16;
 		CRm = (opcode & 0xf);
-		
+
 		/* MCRR */
 		if ((opcode & 0x0ff00000) == 0x0c400000)
 		{
 			instruction->type = ARM_MCRR;
 			mnemonic = "MCRR";
 		}
-		
+
 		/* MRRC */
 		if ((opcode & 0x0ff00000) == 0x0c500000)
 		{
 			instruction->type = ARM_MRRC;
 			mnemonic = "MRRC";
 		}
-		
+
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, %x, r%i, r%i, c%i",
 				 address, opcode, mnemonic, COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm);
 	}
@@ -175,11 +175,11 @@ int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, uint32_t address, arm_instructio
 		uint8_t U, N;
 		char *mnemonic;
 		char addressing_mode[32];
-		
+
 		CRd = (opcode & 0xf000) >> 12;
 		Rn = (opcode & 0xf0000) >> 16;
 		offset = (opcode & 0xff);
-		
+
 		/* load/store */
 		if (opcode & 0x00100000)
 		{
@@ -191,10 +191,10 @@ int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, uint32_t address, arm_instructio
 			instruction->type = ARM_STC;
 			mnemonic = "STC";
 		}
-		
+
 		U = (opcode & 0x00800000) >> 23;
 		N = (opcode & 0x00400000) >> 22;
-		
+
 		/* addressing modes */
 		if ((opcode & 0x01200000) == 0x01000000) /* immediate offset */
 			snprintf(addressing_mode, 32, "[r%i, #%s0x%2.2x*4]", Rn, (U) ? "" : "-", offset);
@@ -210,7 +210,7 @@ int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, uint32_t address, arm_instructio
 				 (N) ? "L" : "",
 				 cp_num, CRd, addressing_mode);
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -222,14 +222,14 @@ int evaluate_cdp_mcr_mrc(uint32_t opcode, uint32_t address, arm_instruction_t *i
 	char* cond;
 	char* mnemonic;
 	uint8_t cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2;
-	
+
 	cond = ((opcode & 0xf0000000) == 0xf0000000) ? "2" : COND(opcode);
 	cp_num = (opcode & 0xf00) >> 8;
 	CRd_Rd = (opcode & 0xf000) >> 12;
 	CRn = (opcode & 0xf0000) >> 16;
 	CRm = (opcode & 0xf);
 	opcode_2 = (opcode & 0xe0) >> 5;
-	
+
 	/* CDP or MRC/MCR */
 	if (opcode & 0x00000010) /* bit 4 set -> MRC/MCR */
 	{
@@ -243,9 +243,9 @@ int evaluate_cdp_mcr_mrc(uint32_t opcode, uint32_t address, arm_instruction_t *i
 			instruction->type = ARM_MCR;
 			mnemonic = "MCR";
 		}
-		
+
 		opcode_1 = (opcode & 0x00e00000) >> 21;
-		
+
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, r%i, c%i, c%i, 0x%2.2x",
 				 address, opcode, mnemonic, cond,
 				 cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2);
@@ -254,14 +254,14 @@ int evaluate_cdp_mcr_mrc(uint32_t opcode, uint32_t address, arm_instruction_t *i
 	{
 		instruction->type = ARM_CDP;
 		mnemonic = "CDP";
-		
+
 		opcode_1 = (opcode & 0x00f00000) >> 20;
-		
+
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, c%i, c%i, c%i, 0x%2.2x",
 				 address, opcode, mnemonic, cond,
 				 cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2);
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -273,7 +273,7 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 	char *operation; /* "LDR" or "STR" */
 	char *suffix; /* "", "B", "T", "BT" */
 	char offset[32];
-	
+
 	/* examine flags */
 	I = (opcode & 0x02000000) >> 25;
 	P = (opcode & 0x01000000) >> 24;
@@ -281,13 +281,13 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 	B = (opcode & 0x00400000) >> 22;
 	W = (opcode & 0x00200000) >> 21;
 	L = (opcode & 0x00100000) >> 20;
-	
+
 	/* target register */
 	Rd = (opcode & 0xf000) >> 12;
-	
+
 	/* base register */
 	Rn = (opcode & 0xf0000) >> 16;
-	
+
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = Rn;
 	instruction->info.load_store.U = U;
@@ -297,7 +297,7 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 		operation = "LDR";
 	else
 		operation = "STR";
-	
+
 	/* determine instruction type and suffix */
 	if (B)
 	{
@@ -337,7 +337,7 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			suffix = "";
 		}
 	}
-	
+
 	if (!I) /* #+-<offset_12> */
 	{
 		uint32_t offset_12 = (opcode & 0xfff);
@@ -345,7 +345,7 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			snprintf(offset, 32, ", #%s0x%" PRIx32 "", (U) ? "" : "-", offset_12);
 		else
 			snprintf(offset, 32, "%s", "");
-		
+
 		instruction->info.load_store.offset_mode = 0;
 		instruction->info.load_store.offset.offset = offset_12;
 	}
@@ -353,15 +353,15 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 	{
 		uint8_t shift_imm, shift;
 		uint8_t Rm;
-		
+
 		shift_imm = (opcode & 0xf80) >> 7;
 		shift = (opcode & 0x60) >> 5;
 		Rm = (opcode & 0xf);
-		
+
 		/* LSR encodes a shift by 32 bit as 0x0 */
 		if ((shift == 0x1) && (shift_imm == 0x0))
 			shift_imm = 0x20;
-		
+
 		/* ASR encodes a shift by 32 bit as 0x0 */
 		if ((shift == 0x2) && (shift_imm == 0x0))
 			shift_imm = 0x20;
@@ -369,7 +369,7 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 		/* ROR by 32 bit is actually a RRX */
 		if ((shift == 0x3) && (shift_imm == 0x0))
 			shift = 0x4;
-		
+
 		instruction->info.load_store.offset_mode = 1;
 		instruction->info.load_store.offset.reg.Rm = Rm;
 		instruction->info.load_store.offset.reg.shift = shift;
@@ -401,7 +401,7 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			}
 		}
 	}
-	
+
 	if (P == 1)
 	{
 		if (W == 0) /* offset */
@@ -409,7 +409,7 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]",
 					 address, opcode, operation, COND(opcode), suffix,
 					 Rd, Rn, offset);
-			
+
 			instruction->info.load_store.index_mode = 0;
 		}
 		else /* pre-indexed */
@@ -417,7 +417,7 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]!",
 					 address, opcode, operation, COND(opcode), suffix,
 					 Rd, Rn, offset);
-			
+
 			instruction->info.load_store.index_mode = 1;
 		}
 	}
@@ -426,10 +426,10 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i]%s",
 				 address, opcode, operation, COND(opcode), suffix,
 				 Rd, Rn, offset);
-		
+
 		instruction->info.load_store.index_mode = 2;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -441,7 +441,7 @@ int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_
 	char *operation; /* "LDR" or "STR" */
 	char *suffix; /* "H", "SB", "SH", "D" */
 	char offset[32];
-	
+
 	/* examine flags */
 	P = (opcode & 0x01000000) >> 24;
 	U = (opcode & 0x00800000) >> 23;
@@ -450,17 +450,17 @@ int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_
 	L = (opcode & 0x00100000) >> 20;
 	S = (opcode & 0x00000040) >> 6;
 	H = (opcode & 0x00000020) >> 5;
-	
+
 	/* target register */
 	Rd = (opcode & 0xf000) >> 12;
-	
+
 	/* base register */
 	Rn = (opcode & 0xf0000) >> 16;
-	
+
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = Rn;
 	instruction->info.load_store.U = U;
-	
+
 	/* determine instruction type and suffix */
 	if (S) /* signed */
 	{
@@ -508,12 +508,12 @@ int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_
 			instruction->type = ARM_STRH;
 		}
 	}
-	
+
 	if (I) /* Immediate offset/index (#+-<offset_8>)*/
 	{
 		uint32_t offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
 		snprintf(offset, 32, "#%s0x%" PRIx32 "", (U) ? "" : "-", offset_8);
-		
+
 		instruction->info.load_store.offset_mode = 0;
 		instruction->info.load_store.offset.offset = offset_8;
 	}
@@ -522,13 +522,13 @@ int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_
 		uint8_t Rm;
 		Rm = (opcode & 0xf);
 		snprintf(offset, 32, "%sr%i", (U) ? "" : "-", Rm);
-		
+
 		instruction->info.load_store.offset_mode = 1;
 		instruction->info.load_store.offset.reg.Rm = Rm;
 		instruction->info.load_store.offset.reg.shift = 0x0;
 		instruction->info.load_store.offset.reg.shift_imm = 0x0;
 	}
-	
+
 	if (P == 1)
 	{
 		if (W == 0) /* offset */
@@ -536,7 +536,7 @@ int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]",
 					 address, opcode, operation, COND(opcode), suffix,
 					 Rd, Rn, offset);
-			
+
 			instruction->info.load_store.index_mode = 0;
 		}
 		else /* pre-indexed */
@@ -544,7 +544,7 @@ int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]!",
 					 address, opcode, operation, COND(opcode), suffix,
 					 Rd, Rn, offset);
-		
+
 			instruction->info.load_store.index_mode = 1;
 		}
 	}
@@ -553,10 +553,10 @@ int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i], %s",
 				 address, opcode, operation, COND(opcode), suffix,
 				 Rd, Rn, offset);
-	
+
 		instruction->info.load_store.index_mode = 2;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -571,7 +571,7 @@ int evaluate_ldm_stm(uint32_t opcode, uint32_t address, arm_instruction_t *instr
 	char *reg_list_p;
 	int i;
 	int first_reg = 1;
-	
+
 	P = (opcode & 0x01000000) >> 24;
 	U = (opcode & 0x00800000) >> 23;
 	S = (opcode & 0x00400000) >> 22;
@@ -579,12 +579,12 @@ int evaluate_ldm_stm(uint32_t opcode, uint32_t address, arm_instruction_t *instr
 	L = (opcode & 0x00100000) >> 20;
 	register_list = (opcode & 0xffff);
 	Rn = (opcode & 0xf0000) >> 16;
-	
+
 	instruction->info.load_store_multiple.Rn = Rn;
 	instruction->info.load_store_multiple.register_list = register_list;
 	instruction->info.load_store_multiple.S = S;
 	instruction->info.load_store_multiple.W = W;
-	
+
 	if (L)
 	{
 		instruction->type = ARM_LDM;
@@ -595,7 +595,7 @@ int evaluate_ldm_stm(uint32_t opcode, uint32_t address, arm_instruction_t *instr
 		instruction->type = ARM_STM;
 		mnemonic = "STM";
 	}
-	
+
 	if (P)
 	{
 		if (U)
@@ -622,7 +622,7 @@ int evaluate_ldm_stm(uint32_t opcode, uint32_t address, arm_instruction_t *instr
 			addressing_mode = "DA";
 		}
 	}
-	
+
 	reg_list_p = reg_list;
 	for (i = 0; i <= 15; i++)
 	{
@@ -639,11 +639,11 @@ int evaluate_ldm_stm(uint32_t opcode, uint32_t address, arm_instruction_t *instr
 			}
 		}
 	}
-	
+
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i%s, {%s}%s",
 			 address, opcode, mnemonic, COND(opcode), addressing_mode,
 			 Rn, (W) ? "!" : "", reg_list, (S) ? "^" : "");
-	
+
 	return ERROR_OK;
 }
 
@@ -662,7 +662,7 @@ int evaluate_mul_and_extra_ld_st(uint32_t opcode, uint32_t address, arm_instruct
 			Rn = (opcode & 0xf000) >> 12;
 			Rd = (opcode & 0xf0000) >> 16;
 			S = (opcode & 0x00100000) >> 20;
-			
+
 			/* examine A bit (accumulate) */
 			if (opcode & 0x00200000)
 			{
@@ -676,10 +676,10 @@ int evaluate_mul_and_extra_ld_st(uint32_t opcode, uint32_t address, arm_instruct
 				snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMUL%s%s r%i, r%i, r%i",
 						 address, opcode, COND(opcode), (S) ? "S" : "", Rd, Rm, Rs);
 			}
-			
+
 			return ERROR_OK;
 		}
-		
+
 		/* Multiply (accumulate) long */
 		if ((opcode & 0x0f800000) == 0x00800000)
 		{
@@ -690,7 +690,7 @@ int evaluate_mul_and_extra_ld_st(uint32_t opcode, uint32_t address, arm_instruct
 			RdHi = (opcode & 0xf000) >> 12;
 			RdLow = (opcode & 0xf0000) >> 16;
 			S = (opcode & 0x00100000) >> 20;
-			
+
 			switch ((opcode & 0x00600000) >> 21)
 			{
 				case 0x0:
@@ -710,14 +710,14 @@ int evaluate_mul_and_extra_ld_st(uint32_t opcode, uint32_t address, arm_instruct
 					mnemonic = "SMLAL";
 					break;
 			}
-			
+
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, r%i, r%i",
 						address, opcode, mnemonic, COND(opcode), (S) ? "S" : "",
 						RdLow, RdHi, Rm, Rs);
-			
+
 			return ERROR_OK;
 		}
-		
+
 		/* Swap/swap byte */
 		if ((opcode & 0x0f800000) == 0x01000000)
 		{
@@ -725,17 +725,17 @@ int evaluate_mul_and_extra_ld_st(uint32_t opcode, uint32_t address, arm_instruct
 			Rm = opcode & 0xf;
 			Rd = (opcode & 0xf000) >> 12;
 			Rn = (opcode & 0xf0000) >> 16;
-			
+
 			/* examine B flag */
 			instruction->type = (opcode & 0x00400000) ? ARM_SWPB : ARM_SWP;
-			
+
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, [r%i]",
 					 address, opcode, (opcode & 0x00400000) ? "SWPB" : "SWP", COND(opcode), Rd, Rm, Rn);
 			return ERROR_OK;
 		}
-		
+
 	}
-	
+
 	return evaluate_misc_load_store(opcode, address, instruction);
 }
 
@@ -743,18 +743,18 @@ int evaluate_mrs_msr(uint32_t opcode, uint32_t address, arm_instruction_t *instr
 {
 	int R = (opcode & 0x00400000) >> 22;
 	char *PSR = (R) ? "SPSR" : "CPSR";
-		
+
 	/* Move register to status register (MSR) */
 	if (opcode & 0x00200000)
 	{
 		instruction->type = ARM_MSR;
-			
+
 		/* immediate variant */
 		if (opcode & 0x02000000)
 		{
 			uint8_t immediate = (opcode & 0xff);
 			uint8_t rotate = (opcode & 0xf00);
-			
+
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, 0x%8.8" PRIx32 ,
 					 address, opcode, COND(opcode), PSR,
 					 (opcode & 0x10000) ? "c" : "",
@@ -776,19 +776,19 @@ int evaluate_mrs_msr(uint32_t opcode, uint32_t address, arm_instruction_t *instr
 					 Rm
 );
 		}
-		
+
 	}
 	else /* Move status register to register (MRS) */
 	{
 		uint8_t Rd;
-		
+
 		instruction->type = ARM_MRS;
 		Rd = (opcode & 0x0000f000) >> 12;
-			
+
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMRS%s r%i, %s",
 				 address, opcode, COND(opcode), Rd, PSR);
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -800,21 +800,21 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 	{
 		evaluate_mrs_msr(opcode, address, instruction);
 	}
-	
+
 	/* BX */
 	if ((opcode & 0x006000f0) == 0x00200010)
 	{
 		uint8_t Rm;
 		instruction->type = ARM_BX;
 		Rm = opcode & 0xf;
-		
+
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBX%s r%i",
 				 address, opcode, COND(opcode), Rm);
-		
+
 		instruction->info.b_bl_bx_blx.reg_operand = Rm;
 		instruction->info.b_bl_bx_blx.target_address = -1;
 	}
-	
+
 	/* CLZ */
 	if ((opcode & 0x006000f0) == 0x00600010)
 	{
@@ -826,21 +826,21 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tCLZ%s r%i, r%i",
 				 address, opcode, COND(opcode), Rd, Rm);
 	}
-	
+
 	/* BLX(2) */
 	if ((opcode & 0x006000f0) == 0x00200030)
 	{
 		uint8_t Rm;
 		instruction->type = ARM_BLX;
 		Rm = opcode & 0xf;
-		
+
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX%s r%i",
 				 address, opcode, COND(opcode), Rm);
-				 
+
 		instruction->info.b_bl_bx_blx.reg_operand = Rm;
 		instruction->info.b_bl_bx_blx.target_address = -1;
 	}
-	
+
 	/* Enhanced DSP add/subtracts */
 	if ((opcode & 0x0000000f0) == 0x00000050)
 	{
@@ -849,7 +849,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 		Rm = opcode & 0xf;
 		Rd = (opcode & 0xf000) >> 12;
 		Rn = (opcode & 0xf0000) >> 16;
-		
+
 		switch ((opcode & 0x00600000) >> 21)
 		{
 			case 0x0:
@@ -869,28 +869,28 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 				mnemonic = "QDSUB";
 				break;
 		}
-		
+
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, r%i",
 				 address, opcode, mnemonic, COND(opcode), Rd, Rm, Rn);
 	}
-	
+
 	/* Software breakpoints */
 	if ((opcode & 0x0000000f0) == 0x00000070)
 	{
 		uint32_t immediate;
 		instruction->type = ARM_BKPT;
 		immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
-		
+
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBKPT 0x%4.4" PRIx32 "",
-				 address, opcode, immediate);	
+				 address, opcode, immediate);
 	}
-	
+
 	/* Enhanced DSP multiplies */
 	if ((opcode & 0x000000090) == 0x00000080)
 	{
 		int x = (opcode & 0x20) >> 5;
 		int y = (opcode & 0x40) >> 6;
-		
+
 		/* SMLA < x><y> */
 		if ((opcode & 0x00600000) == 0x00000000)
 		{
@@ -900,12 +900,12 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			Rm = (opcode & 0xf);
 			Rs = (opcode & 0xf00) >> 8;
 			Rn = (opcode & 0xf000) >> 12;
-			
+
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i",
 					 address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
 					 Rd, Rm, Rs, Rn);
 		}
-		
+
 		/* SMLAL < x><y> */
 		if ((opcode & 0x00600000) == 0x00400000)
 		{
@@ -915,12 +915,12 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			RdLow = (opcode & 0xf000) >> 12;
 			Rm = (opcode & 0xf);
 			Rs = (opcode & 0xf00) >> 8;
-			
+
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i",
 					 address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
 					 RdLow, RdHi, Rm, Rs);
 		}
-		
+
 		/* SMLAW < y> */
 		if (((opcode & 0x00600000) == 0x00100000) && (x == 0))
 		{
@@ -935,7 +935,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 					 address, opcode, (y) ? "T" : "B", COND(opcode),
 					 Rd, Rm, Rs, Rn);
 		}
-		
+
 		/* SMUL < x><y> */
 		if ((opcode & 0x00600000) == 0x00300000)
 		{
@@ -944,12 +944,12 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			Rd = (opcode & 0xf0000) >> 16;
 			Rm = (opcode & 0xf);
 			Rs = (opcode & 0xf00) >> 8;
-			
+
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s%s r%i, r%i, r%i",
 					 address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
 					 Rd, Rm, Rs);
 		}
-		
+
 		/* SMULW < y> */
 		if (((opcode & 0x00600000) == 0x00100000) && (x == 1))
 		{
@@ -958,13 +958,13 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			Rd = (opcode & 0xf0000) >> 16;
 			Rm = (opcode & 0xf);
 			Rs = (opcode & 0xf00) >> 8;
-			
+
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s r%i, r%i, r%i",
 					 address, opcode, (y) ? "T" : "B", COND(opcode),
 					 Rd, Rm, Rs);
 		}
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -973,14 +973,14 @@ int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *ins
 	uint8_t I, op, S, Rn, Rd;
 	char *mnemonic = NULL;
 	char shifter_operand[32];
-	
+
 	I = (opcode & 0x02000000) >> 25;
 	op = (opcode & 0x01e00000) >> 21;
 	S = (opcode & 0x00100000) >> 20;
-	
+
 	Rd = (opcode & 0xf000) >> 12;
 	Rn = (opcode & 0xf0000) >> 16;
-	
+
 	instruction->info.data_proc.Rd = Rd;
 	instruction->info.data_proc.Rn = Rn;
 	instruction->info.data_proc.S = S;
@@ -1052,17 +1052,17 @@ int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *ins
 			mnemonic = "MVN";
 			break;
 	}
-	
+
 	if (I) /* immediate shifter operand (#<immediate>)*/
 	{
 		uint8_t immed_8 = opcode & 0xff;
 		uint8_t rotate_imm = (opcode & 0xf00) >> 8;
 		uint32_t immediate;
-		
+
 		immediate = ror(immed_8, rotate_imm * 2);
-		
+
 		snprintf(shifter_operand, 32, "#0x%" PRIx32 "", immediate);
-		
+
 		instruction->info.data_proc.variant = 0;
 		instruction->info.data_proc.shifter_operand.immediate.immediate = immediate;
 	}
@@ -1071,7 +1071,7 @@ int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *ins
 		uint8_t shift, Rm;
 		shift = (opcode & 0x60) >> 5;
 		Rm = (opcode & 0xf);
-		
+
 		if ((opcode & 0x10) != 0x10) /* Immediate shifts ("<Rm>" or "<Rm>, <shift> #<shift_immediate>") */
 		{
 			uint8_t shift_imm;
@@ -1081,11 +1081,11 @@ int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *ins
 			instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
 			instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = shift_imm;
 			instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift;
-		
+
 			/* LSR encodes a shift by 32 bit as 0x0 */
 			if ((shift == 0x1) && (shift_imm == 0x0))
 				shift_imm = 0x20;
-		
+
 			/* ASR encodes a shift by 32 bit as 0x0 */
 			if ((shift == 0x2) && (shift_imm == 0x0))
 				shift_imm = 0x20;
@@ -1093,7 +1093,7 @@ int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *ins
 			/* ROR by 32 bit is actually a RRX */
 			if ((shift == 0x3) && (shift_imm == 0x0))
 				shift = 0x4;
-			
+
 			if ((shift_imm == 0x0) && (shift == 0x0))
 			{
 				snprintf(shifter_operand, 32, "r%i", Rm);
@@ -1125,12 +1125,12 @@ int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *ins
 		else /* Register shifts ("<Rm>, <shift> <Rs>") */
 		{
 			uint8_t Rs = (opcode & 0xf00) >> 8;
-			
+
 			instruction->info.data_proc.variant = 2;
 			instruction->info.data_proc.shifter_operand.register_shift.Rm = Rm;
 			instruction->info.data_proc.shifter_operand.register_shift.Rs = Rs;
 			instruction->info.data_proc.shifter_operand.register_shift.shift = shift;
-			
+
 			if (shift == 0x0) /* LSL */
 			{
 				snprintf(shifter_operand, 32, "r%i, LSL r%i", Rm, Rs);
@@ -1149,7 +1149,7 @@ int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *ins
 			}
 		}
 	}
-	
+
 	if ((op < 0x8) || (op == 0xc) || (op == 0xe)) /* <opcode3>{<cond>}{S} <Rd>, <Rn>, <shifter_operand> */
 	{
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, %s",
@@ -1171,23 +1171,23 @@ int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *ins
 				 address, opcode, mnemonic, COND(opcode),
 				 Rn, shifter_operand);
 	}
-	
+
 	return ERROR_OK;
 }
-		
+
 int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	/* clear fields, to avoid confusion */
 	memset(instruction, 0, sizeof(arm_instruction_t));
 	instruction->opcode = opcode;
-	
+
 	/* catch opcodes with condition field [31:28] = b1111 */
 	if ((opcode & 0xf0000000) == 0xf0000000)
 	{
 		/* Undefined instruction (or ARMv5E cache preload PLD) */
 		if ((opcode & 0x08000000) == 0x00000000)
 			return evaluate_pld(opcode, address, instruction);
-		
+
 		/* Undefined instruction */
 		if ((opcode & 0x0e000000) == 0x08000000)
 		{
@@ -1195,24 +1195,24 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
 			return ERROR_OK;
 		}
-		
+
 		/* Branch and branch with link and change to Thumb */
 		if ((opcode & 0x0e000000) == 0x0a000000)
 			return evaluate_blx_imm(opcode, address, instruction);
-		
+
 		/* Extended coprocessor opcode space (ARMv5 and higher)*/
 		/* Coprocessor load/store and double register transfers */
 		if ((opcode & 0x0e000000) == 0x0c000000)
 			return evaluate_ldc_stc_mcrr_mrrc(opcode, address, instruction);
-		
+
 		/* Coprocessor data processing */
 		if ((opcode & 0x0f000100) == 0x0c000000)
 			return evaluate_cdp_mcr_mrc(opcode, address, instruction);
-		
+
 		/* Coprocessor register transfers */
 		if ((opcode & 0x0f000010) == 0x0c000010)
 			return evaluate_cdp_mcr_mrc(opcode, address, instruction);
-		
+
 		/* Undefined instruction */
 		if ((opcode & 0x0f000000) == 0x0f000000)
 		{
@@ -1221,21 +1221,21 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			return ERROR_OK;
 		}
 	}
-	
+
 	/* catch opcodes with [27:25] = b000 */
 	if ((opcode & 0x0e000000) == 0x00000000)
 	{
 		/* Multiplies, extra load/stores */
 		if ((opcode & 0x00000090) == 0x00000090)
 			return evaluate_mul_and_extra_ld_st(opcode, address, instruction);
-		
+
 		/* Miscellaneous instructions */
 		if ((opcode & 0x0f900000) == 0x01000000)
 			return evaluate_misc_instr(opcode, address, instruction);
-		
+
 		return evaluate_data_proc(opcode, address, instruction);
 	}
-	
+
 	/* catch opcodes with [27:25] = b001 */
 	if ((opcode & 0x0e000000) == 0x02000000)
 	{
@@ -1246,22 +1246,22 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
 			return ERROR_OK;
 		}
-				
+
 		/* Move immediate to status register */
 		if ((opcode & 0x0fb00000) == 0x03200000)
 			return evaluate_mrs_msr(opcode, address, instruction);
-		
+
 		return evaluate_data_proc(opcode, address, instruction);
 
 	}
-	
+
 	/* catch opcodes with [27:25] = b010 */
 	if ((opcode & 0x0e000000) == 0x04000000)
 	{
 		/* Load/store immediate offset */
 		return evaluate_load_store(opcode, address, instruction);
 	}
-	
+
 	/* catch opcodes with [27:25] = b011 */
 	if ((opcode & 0x0e000000) == 0x06000000)
 	{
@@ -1272,49 +1272,49 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *in
 			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
 			return ERROR_OK;
 		}
-		
+
 		/* Load/store register offset */
 		return evaluate_load_store(opcode, address, instruction);
 
 	}
-	
+
 	/* catch opcodes with [27:25] = b100 */
 	if ((opcode & 0x0e000000) == 0x08000000)
 	{
 		/* Load/store multiple */
 		return evaluate_ldm_stm(opcode, address, instruction);
 	}
-	
+
 	/* catch opcodes with [27:25] = b101 */
 	if ((opcode & 0x0e000000) == 0x0a000000)
 	{
 		/* Branch and branch with link */
 		return evaluate_b_bl(opcode, address, instruction);
 	}
-	
+
 	/* catch opcodes with [27:25] = b110 */
 	if ((opcode & 0x0e000000) == 0x0a000000)
 	{
 		/* Coprocessor load/store and double register transfers */
 		return evaluate_ldc_stc_mcrr_mrrc(opcode, address, instruction);
 	}
-	
+
 	/* catch opcodes with [27:25] = b111 */
 	if ((opcode & 0x0e000000) == 0x0e000000)
 	{
 		/* Software interrupt */
 		if ((opcode & 0x0f000000) == 0x0f000000)
 			return evaluate_swi(opcode, address, instruction);
-		
+
 		/* Coprocessor data processing */
 		if ((opcode & 0x0f000010) == 0x0e000000)
 			return evaluate_cdp_mcr_mrc(opcode, address, instruction);
-		
+
 		/* Coprocessor register transfers */
 		if ((opcode & 0x0f000010) == 0x0e000010)
 			return evaluate_cdp_mcr_mrc(opcode, address, instruction);
 	}
-	
+
 	LOG_ERROR("should never reach this point");
 	return -1;
 }
@@ -1325,11 +1325,11 @@ int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
 	uint32_t opc = (opcode >> 11) & 0x3;
 	uint32_t target_address;
 	char *mnemonic = NULL;
-	
+
 	/* sign extend 11-bit offset */
 	if (((opc == 0) || (opc == 2)) && (offset & 0x00000400))
 		offset = 0xfffff800 | offset;
-	
+
 	target_address = address + 4 + (offset << 1);
 
 	switch (opc)
@@ -1359,7 +1359,7 @@ int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
 	/* TODO: deals correctly with dual opcodes BL/BLX ... */
 
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s 0x%8.8" PRIx32 , address, opcode,mnemonic, target_address);
-	
+
 	instruction->info.b_bl_bx_blx.reg_operand = -1;
 	instruction->info.b_bl_bx_blx.target_address = target_address;
 
@@ -1374,7 +1374,7 @@ int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
 	uint32_t opc = opcode & (1 << 9);
 	uint32_t reg_imm  = opcode & (1 << 10);
 	char *mnemonic;
-	
+
 	if (opc)
 	{
 		instruction->type = ARM_SUB;
@@ -1385,7 +1385,7 @@ int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
 		instruction->type = ARM_ADD;
 		mnemonic = "ADDS";
 	}
-	
+
 	instruction->info.data_proc.Rd = Rd;
 	instruction->info.data_proc.Rn = Rn;
 	instruction->info.data_proc.S = 1;
@@ -1415,7 +1415,7 @@ int evaluate_shift_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_
 	uint8_t imm = (opcode >> 6) & 0x1f;
 	uint8_t opc = (opcode >> 11) & 0x3;
 	char *mnemonic = NULL;
-	
+
 	switch (opc)
 	{
 		case 0:
@@ -1458,13 +1458,13 @@ int evaluate_data_proc_imm_thumb(uint16_t opcode, uint32_t address, arm_instruct
 	uint8_t Rd = (opcode >> 8) & 0x7;
 	uint32_t opc = (opcode >> 11) & 0x3;
 	char *mnemonic = NULL;
-	
+
 	instruction->info.data_proc.Rd = Rd;
 	instruction->info.data_proc.Rn = Rd;
 	instruction->info.data_proc.S = 1;
 	instruction->info.data_proc.variant = 0; /*immediate*/
 	instruction->info.data_proc.shifter_operand.immediate.immediate = imm;
-	
+
 	switch (opc)
 	{
 		case 0:
@@ -1486,7 +1486,7 @@ int evaluate_data_proc_imm_thumb(uint16_t opcode, uint32_t address, arm_instruct
 			mnemonic = "SUBS";
 			break;
 	}
-	
+
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, #0x%02x" ,
 				 address, opcode, mnemonic, Rd, imm);
 
@@ -1497,15 +1497,15 @@ int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
 {
 	uint8_t high_reg, op, Rm, Rd,H1,H2;
 	char *mnemonic = NULL;
-	
+
 	high_reg = (opcode & 0x0400) >> 10;
 	op = (opcode & 0x03C0) >> 6;
-	
+
 	Rd = (opcode & 0x0007);
 	Rm = (opcode & 0x0038) >> 3;
 	H1 = (opcode & 0x0080) >> 7;
 	H2 = (opcode & 0x0040) >> 6;
-	
+
 	instruction->info.data_proc.Rd = Rd;
 	instruction->info.data_proc.Rn = Rd;
 	instruction->info.data_proc.S = (!high_reg || (instruction->type == ARM_CMP));
@@ -1517,7 +1517,7 @@ int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
 		Rd |= H1 << 3;
 		Rm |= H2 << 3;
 		op >>= 2;
-	
+
 		switch (op)
 		{
 			case 0x0:
@@ -1552,7 +1552,7 @@ int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
 					instruction->type = ARM_UNDEFINED_INSTRUCTION;
 					snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
 				}
-				return ERROR_OK;	
+				return ERROR_OK;
 				break;
 		}
 	}
@@ -1655,7 +1655,7 @@ int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
 int evaluate_load_literal_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	uint32_t immediate;
-	uint8_t Rd = (opcode >> 8) & 0x7; 
+	uint8_t Rd = (opcode >> 8) & 0x7;
 
 	instruction->type = ARM_LDR;
 	immediate = opcode & 0x000000ff;
@@ -1673,10 +1673,10 @@ int evaluate_load_literal_thumb(uint16_t opcode, uint32_t address, arm_instructi
 
 int evaluate_load_store_reg_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-	uint8_t Rd = (opcode >> 0) & 0x7; 
-	uint8_t Rn = (opcode >> 3) & 0x7; 
-	uint8_t Rm = (opcode >> 6) & 0x7; 
-	uint8_t opc = (opcode >> 9) & 0x7; 
+	uint8_t Rd = (opcode >> 0) & 0x7;
+	uint8_t Rn = (opcode >> 3) & 0x7;
+	uint8_t Rm = (opcode >> 6) & 0x7;
+	uint8_t opc = (opcode >> 9) & 0x7;
 	char *mnemonic = NULL;
 
 	switch (opc)
@@ -1716,7 +1716,7 @@ int evaluate_load_store_reg_thumb(uint16_t opcode, uint32_t address, arm_instruc
 	}
 
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [r%i, r%i]", address, opcode, mnemonic, Rd, Rn, Rm);
-	
+
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = Rn;
 	instruction->info.load_store.index_mode = 0; /*offset*/
@@ -1729,8 +1729,8 @@ int evaluate_load_store_reg_thumb(uint16_t opcode, uint32_t address, arm_instruc
 int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	uint32_t offset = (opcode >> 6) & 0x1f;
-	uint8_t Rd = (opcode >> 0) & 0x7; 
-	uint8_t Rn = (opcode >> 3) & 0x7; 
+	uint8_t Rd = (opcode >> 0) & 0x7;
+	uint8_t Rn = (opcode >> 3) & 0x7;
 	uint32_t L = opcode & (1 << 11);
 	uint32_t B = opcode & (1 << 12);
 	char *mnemonic;
@@ -1760,7 +1760,7 @@ int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruc
 	}
 
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
-	
+
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = Rn;
 	instruction->info.load_store.index_mode = 0; /*offset*/
@@ -1773,7 +1773,7 @@ int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruc
 int evaluate_load_store_stack_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	uint32_t offset = opcode  & 0xff;
-	uint8_t Rd = (opcode >> 8) & 0x7; 
+	uint8_t Rd = (opcode >> 8) & 0x7;
 	uint32_t L = opcode & (1 << 11);
 	char *mnemonic;
 
@@ -1789,7 +1789,7 @@ int evaluate_load_store_stack_thumb(uint16_t opcode, uint32_t address, arm_instr
 	}
 
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [SP, #0x%" PRIx32 "]", address, opcode, mnemonic, Rd, offset*4);
-	
+
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = 13 /*SP*/;
 	instruction->info.load_store.index_mode = 0; /*offset*/
@@ -1802,13 +1802,13 @@ int evaluate_load_store_stack_thumb(uint16_t opcode, uint32_t address, arm_instr
 int evaluate_add_sp_pc_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	uint32_t imm = opcode  & 0xff;
-	uint8_t Rd = (opcode >> 8) & 0x7; 
+	uint8_t Rd = (opcode >> 8) & 0x7;
 	uint8_t Rn;
 	uint32_t SP = opcode & (1 << 11);
 	char *reg_name;
 
 	instruction->type = ARM_ADD;
-	
+
 	if (SP)
 	{
 		reg_name = "SP";
@@ -1836,7 +1836,7 @@ int evaluate_adjust_stack_thumb(uint16_t opcode, uint32_t address, arm_instructi
 	uint8_t opc = opcode & (1 << 7);
 	char *mnemonic;
 
-	
+
 	if (opc)
 	{
 		instruction->type = ARM_SUB;
@@ -1861,7 +1861,7 @@ int evaluate_adjust_stack_thumb(uint16_t opcode, uint32_t address, arm_instructi
 int evaluate_breakpoint_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	uint32_t imm = opcode  & 0xff;
-	
+
 	instruction->type = ARM_BKPT;
 
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBKPT 0x%02" PRIx32 "", address, opcode, imm);
@@ -1880,7 +1880,7 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in
 	char *reg_names_p;
 	char *mnemonic;
 	char ptr_name[7] = "";
-	int i;	
+	int i;
 
 	if ((opcode & 0xf000) == 0xc000)
 	{ /* generic load/store multiple */
@@ -1958,12 +1958,12 @@ int evaluate_cond_branch_thumb(uint16_t opcode, uint32_t address, arm_instructio
 	/* sign extend 8-bit offset */
 	if (offset & 0x00000080)
 		offset = 0xffffff00 | offset;
-	
+
 	target_address = address + 4 + (offset << 1);
 
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tB%s 0x%8.8" PRIx32 , address, opcode,
 			 arm_condition_strings[cond], target_address);
-	
+
 	instruction->type = ARM_B;
 	instruction->info.b_bl_bx_blx.reg_operand = -1;
 	instruction->info.b_bl_bx_blx.target_address = target_address;
@@ -1976,7 +1976,7 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *
 	/* clear fields, to avoid confusion */
 	memset(instruction, 0, sizeof(arm_instruction_t));
 	instruction->opcode = opcode;
-	
+
 	if ((opcode & 0xe000) == 0x0000)
 	{
 		/* add/substract register or immediate */
@@ -1986,19 +1986,19 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *
 		else
 			return evaluate_shift_imm_thumb(opcode, address, instruction);
 	}
-	
+
 	/* Add/substract/compare/move immediate */
 	if ((opcode & 0xe000) == 0x2000)
 	{
 		return evaluate_data_proc_imm_thumb(opcode, address, instruction);
 	}
-	
+
 	/* Data processing instructions */
 	if ((opcode & 0xf800) == 0x4000)
 	{
 		return evaluate_data_proc_thumb(opcode, address, instruction);
 	}
-	
+
 	/* Load from literal pool */
 	if ((opcode & 0xf800) == 0x4800)
 	{
@@ -2017,7 +2017,7 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *
 	{
 		return evaluate_load_store_imm_thumb(opcode, address, instruction);
 	}
-	
+
 	/* Load/Store from/to stack */
 	if ((opcode & 0xf000) == 0x9000)
 	{
@@ -2058,7 +2058,7 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *
 	{
 		return evaluate_cond_branch_thumb(opcode, address, instruction);
 	}
-	
+
 	if ((opcode & 0xe000) == 0xe000)
 	{
 		/* Undefined instructions */
diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index 00c4b295..a8b9aba1 100644
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -25,13 +25,13 @@
 enum arm_instruction_type
 {
 	ARM_UNKNOWN_INSTUCTION,
-	
+
 	/* Branch instructions */
 	ARM_B,
 	ARM_BL,
 	ARM_BX,
 	ARM_BLX,
-	
+
 	/* Data processing instructions */
 	ARM_AND,
 	ARM_EOR,
@@ -49,32 +49,32 @@ enum arm_instruction_type
 	ARM_MOV,
 	ARM_BIC,
 	ARM_MVN,
-	
+
 	/* Load/store instructions */
 	ARM_LDR,
 	ARM_LDRB,
 	ARM_LDRT,
 	ARM_LDRBT,
-	
+
 	ARM_LDRH,
 	ARM_LDRSB,
 	ARM_LDRSH,
-	
+
 	ARM_LDM,
 
 	ARM_STR,
 	ARM_STRB,
 	ARM_STRT,
 	ARM_STRBT,
-	
+
 	ARM_STRH,
-	
+
 	ARM_STM,
-	
+
 	/* Status register access instructions */
 	ARM_MRS,
 	ARM_MSR,
-	
+
 	/* Multiply instructions */
 	ARM_MUL,
 	ARM_MLA,
@@ -82,25 +82,25 @@ enum arm_instruction_type
 	ARM_SMLAL,
 	ARM_UMULL,
 	ARM_UMLAL,
-	
+
 	/* Miscellaneous instructions */
 	ARM_CLZ,
-	
+
 	/* Exception generating instructions */
 	ARM_BKPT,
 	ARM_SWI,
-	
+
 	/* Coprocessor instructions */
 	ARM_CDP,
 	ARM_LDC,
 	ARM_STC,
 	ARM_MCR,
 	ARM_MRC,
-	
+
 	/* Semaphore instructions */
 	ARM_SWP,
 	ARM_SWPB,
-	
+
 	/* Enhanced DSP extensions */
 	ARM_MCRR,
 	ARM_MRRC,
@@ -184,7 +184,7 @@ typedef struct arm_instruction_s
 	enum arm_instruction_type type;
 	char text[128];
 	uint32_t opcode;
-	
+
 	union {
 		arm_b_bl_bx_blx_instr_t b_bl_bx_blx;
 		arm_data_proc_instr_t data_proc;
diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c
index 9df4eeae..7740a1ec 100644
--- a/src/target/arm_jtag.c
+++ b/src/target/arm_jtag.c
@@ -48,7 +48,7 @@ int arm_jtag_set_instr(arm_jtag_t *jtag_info, uint32_t new_instr,  void *no_veri
 		field.out_value = t;
 		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
 		field.in_value = NULL;
-		
+
 
 
 		if (no_verify_capture == NULL)
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 6de9e513..c087b772 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -35,7 +35,7 @@ uint32_t arm_shift(uint8_t shift, uint32_t Rm, uint32_t shift_amount, uint8_t *c
 {
 	uint32_t return_value = 0;
 	shift_amount &= 0xff;
-	
+
 	if (shift == 0x0) /* LSL */
 	{
 		if ((shift_amount > 0) && (shift_amount <= 32))
@@ -118,7 +118,7 @@ uint32_t arm_shift(uint8_t shift, uint32_t Rm, uint32_t shift_amount, uint8_t *c
 			Rm |= 0x80000000;
 		*carry = Rm & 0x1;
 	}
-	
+
 	return return_value;
 }
 
@@ -126,14 +126,14 @@ uint32_t arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_s
 {
 	uint32_t return_value;
 	int instruction_size;
-	
+
 	if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 		instruction_size = 4;
 	else
 		instruction_size = 2;
-	
+
 	*shifter_carry_out = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
-	
+
 	if (variant == 0) /* 32-bit immediate */
 	{
 		return_value = shifter_operand.immediate.immediate;
@@ -141,22 +141,22 @@ uint32_t arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_s
 	else if (variant == 1) /* immediate shift */
 	{
 		uint32_t Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.immediate_shift.Rm).value, 0, 32);
-		
+
 		/* adjust RM in case the PC is being read */
 		if (shifter_operand.immediate_shift.Rm == 15)
 			Rm += 2 * instruction_size;
-		
+
 		return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, shifter_operand.immediate_shift.shift_imm, shifter_carry_out);
 	}
 	else if (variant == 2) /* register shift */
 	{
 		uint32_t Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rm).value, 0, 32);
 		uint32_t Rs = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rs).value, 0, 32);
-		
+
 		/* adjust RM in case the PC is being read */
 		if (shifter_operand.register_shift.Rm == 15)
 			Rm += 2 * instruction_size;
-			
+
 		return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, Rs, shifter_carry_out);
 	}
 	else
@@ -164,7 +164,7 @@ uint32_t arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_s
 		LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
 		return_value = 0xffffffff;
 	}
-	
+
 	return return_value;
 }
 
@@ -251,16 +251,16 @@ int pass_condition(uint32_t cpsr, uint32_t opcode)
 		case 0xe:
 		case 0xf:
 			return 1;
-				
+
 	}
-	
+
 	LOG_ERROR("BUG: should never get here");
 	return 0;
 }
 
 int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode)
 {
-	return pass_condition(cpsr, (opcode & 0x0f00) << 20); 
+	return pass_condition(cpsr, (opcode & 0x0f00) << 20);
 }
 
 /* simulate a single step (if possible)
@@ -274,11 +274,11 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 	arm_instruction_t instruction;
 	int instruction_size;
 	int retval = ERROR_OK;
-	
+
 	if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 	{
 		uint32_t opcode;
-		
+
 		/* get current instruction, and identify it */
 		if ((retval = target_read_u32(target, current_pc, &opcode)) != ERROR_OK)
 		{
@@ -289,7 +289,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			return retval;
 		}
 		instruction_size = 4;
-		
+
 		/* check condition code (for all instructions) */
 		if (!pass_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode))
 		{
@@ -301,14 +301,14 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			{
 				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
 			}
-			
+
 			return ERROR_OK;
 		}
 	}
 	else
 	{
 		uint16_t opcode;
-		
+
 		if ((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK)
 		{
 			return retval;
@@ -318,7 +318,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			return retval;
 			}
 		instruction_size = 2;
-		
+
 		/* check condition code (only for branch instructions) */
 		if ((!thumb_pass_branch_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode)) &&
 			(instruction.type == ARM_B))
@@ -331,33 +331,33 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			{
 				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
 			}
-			
+
 			return ERROR_OK;
 		}
 	}
-	
+
 	/* examine instruction type */
 
 	/* branch instructions */
 	if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
 	{
 		uint32_t target;
-		
+
 		if (instruction.info.b_bl_bx_blx.reg_operand == -1)
 		{
 			target = instruction.info.b_bl_bx_blx.target_address;
 		}
 		else
 		{
-			target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32); 
+			target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32);
 			if (instruction.info.b_bl_bx_blx.reg_operand == 15)
 			{
 				target += 2 * instruction_size;
 			}
 		}
-		
+
 		if (dry_run_pc)
-		{	
+		{
 			*dry_run_pc = target;
 			return ERROR_OK;
 		}
@@ -400,7 +400,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 				}
 				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe);
 			}
-			
+
 			return ERROR_OK;
 		}
 	}
@@ -411,7 +411,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 		uint32_t Rd, Rn, shifter_operand;
 		uint8_t C = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
 		uint8_t carry_out;
-		
+
 		Rd = 0x0;
 		/* ARM_MOV and ARM_MVN does not use Rn */
 		if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
@@ -424,7 +424,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 		/* adjust Rn in case the PC is being read */
 		if (instruction.info.data_proc.Rn == 15)
 			Rn += 2 * instruction_size;
-				
+
 		if (instruction.type == ARM_AND)
 			Rd = Rn & shifter_operand;
 		else if (instruction.type == ARM_EOR)
@@ -451,7 +451,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			Rd = ~shifter_operand;
 		else
 			LOG_WARNING("unhandled instruction type");
-		
+
 		if (dry_run_pc)
 		{
 			if (instruction.info.data_proc.Rd == 15)
@@ -463,7 +463,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			{
 				*dry_run_pc = current_pc + instruction_size;
 			}
-			
+
 			return ERROR_OK;
 		}
 		else
@@ -471,7 +471,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rd).value, 0, 32, Rd);
 			LOG_WARNING("no updating of flags yet");
 
-			if (instruction.info.data_proc.Rd == 15)  
+			if (instruction.info.data_proc.Rd == 15)
 				return ERROR_OK;
 		}
 	}
@@ -493,11 +493,11 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 	{
 		uint32_t load_address = 0, modified_address = 0, load_value;
 		uint32_t Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32);
-		
+
 		/* adjust Rn in case the PC is being read */
 		if (instruction.info.load_store.Rn == 15)
 			Rn += 2 * instruction_size;
-		
+
 		if (instruction.info.load_store.offset_mode == 0)
 		{
 			if (instruction.info.load_store.U)
@@ -512,9 +512,9 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			uint8_t shift = instruction.info.load_store.offset.reg.shift;
 			uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
 			uint8_t carry = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
-			
+
 			offset = arm_shift(shift, Rm, shift_imm, &carry);
-			
+
 			if (instruction.info.load_store.U)
 				modified_address = Rn + offset;
 			else
@@ -524,7 +524,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 		{
 			LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
 		}
-		
+
 		if (instruction.info.load_store.index_mode == 0)
 		{
 			/* offset mode
@@ -544,7 +544,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			 * we load from the unmodified address, and write the modified address back */
 			 load_address = Rn;
 		}
-		
+
 		if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15))
 		{
 			if ((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
@@ -552,7 +552,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 				return retval;
 			}
 		}
-		
+
 		if (dry_run_pc)
 		{
 			if (instruction.info.load_store.Rd == 15)
@@ -564,7 +564,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			{
 				*dry_run_pc = current_pc + instruction_size;
 			}
-			
+
 			return ERROR_OK;
 		}
 		else
@@ -573,9 +573,9 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 				(instruction.info.load_store.index_mode == 2))
 			{
 				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32, modified_address);
-			} 
+			}
 			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rd).value, 0, 32, load_value);
-			
+
 			if (instruction.info.load_store.Rd == 15)
 				return ERROR_OK;
 		}
@@ -593,7 +593,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 			if (instruction.info.load_store_multiple.register_list & (1 << i))
 				bits_set++;
 		}
-		
+
 		switch (instruction.info.load_store_multiple.addressing_mode)
 		{
 			case 0: /* Increment after */
@@ -603,7 +603,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 				Rn = Rn + 4;
 				break;
 			case 2: /* Decrement after */
-				Rn = Rn - (bits_set * 4) + 4; 
+				Rn = Rn - (bits_set * 4) + 4;
 				break;
 			case 3: /* Decrement before */
 				Rn = Rn - (bits_set * 4);
@@ -621,7 +621,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 				Rn += 4;
 			}
 		}
-		
+
 		if (dry_run_pc)
 		{
 			if (instruction.info.load_store_multiple.register_list & 0x8000)
@@ -650,17 +650,17 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 					buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, i).value, 0, 32, load_values[i]);
 				}
 			}
-			
+
 			if (update_cpsr)
 			{
 				uint32_t spsr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32);
 				buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr);
 			}
-			
+
 			/* base register writeback */
 			if (instruction.info.load_store_multiple.W)
-				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn); 
-			
+				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn);
+
 			if (instruction.info.load_store_multiple.register_list & 0x8000)
 				return ERROR_OK;
 		}
@@ -685,12 +685,12 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 				if (instruction.info.load_store_multiple.register_list & (1 << i))
 					bits_set++;
 			}
-			
+
 			if (instruction.info.load_store_multiple.S)
 			{
 				mode = ARMV4_5_MODE_USR;
 			}
-			
+
 			switch (instruction.info.load_store_multiple.addressing_mode)
 			{
 				case 0: /* Increment after */
@@ -700,13 +700,13 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 					Rn = Rn + 4;
 					break;
 				case 2: /* Decrement after */
-					Rn = Rn - (bits_set * 4) + 4; 
+					Rn = Rn - (bits_set * 4) + 4;
 					break;
 				case 3: /* Decrement before */
 					Rn = Rn - (bits_set * 4);
 					break;
 			}
-			
+
 			for (i = 0; i < 16; i++)
 			{
 				if (instruction.info.load_store_multiple.register_list & (1 << i))
@@ -715,11 +715,11 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 					Rn += 4;
 				}
 			}
-			
+
 			/* base register writeback */
 			if (instruction.info.load_store_multiple.W)
-				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn); 
-			
+				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn);
+
 		}
 	}
 	else if (!dry_run_pc)
@@ -728,7 +728,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 		 */
 		return ERROR_ARM_SIMULATOR_NOT_IMPLEMENTED;
 	}
-	
+
 	if (dry_run_pc)
 	{
 		*dry_run_pc = current_pc + instruction_size;
@@ -739,5 +739,5 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 		buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
 		return ERROR_OK;
 	}
-	
+
 }
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 8d2167e5..9861843e 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -339,9 +339,9 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha
 			{
 				armv4_5->full_context(target);
 			}
-			output_len += snprintf(output + output_len, 
-					       128 - output_len, 
-					       "%8s: %8.8" PRIx32 " ", 
+			output_len += snprintf(output + output_len,
+					       128 - output_len,
+					       "%8s: %8.8" PRIx32 " ",
 					       ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
 					       buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
 		}
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index b93dda36..fe8bc3ba 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -543,7 +543,7 @@ int armv7m_register_commands(struct command_context_s *cmd_ctx)
 {
 	command_t *arm_adi_v5_dap_cmd;
 
-	arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");		
+	arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");
 	register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "Displays dap info for ap [num], default currently selected AP");
 	register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "Select a different AP [num] (default 0)");
 	register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", handle_dap_apid_command, COMMAND_EXEC, "Displays id reg from AP [num], default currently selected AP");
@@ -710,7 +710,7 @@ int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, ch
 	apsel = swjdp->apsel;
 	apselsave = swjdp->apsel;
 	if (argc > 0)
-	{	
+	{
 		apsel = strtoul(args[0], NULL, 0);
 	}
 	if (apselsave != apsel)
@@ -745,7 +745,7 @@ extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd,
 	apsel = swjdp->apsel;
 	apselsave = swjdp->apsel;
 	if (argc > 0)
-	{	
+	{
 		apsel = strtoul(args[0], NULL, 0);
 	}
 
@@ -775,7 +775,7 @@ int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char
 
 	apsel = 0;
 	if (argc > 0)
-	{	
+	{
 		apsel = strtoul(args[0], NULL, 0);
 	}
 
@@ -796,7 +796,7 @@ int handle_dap_memaccess_command(struct command_context_s *cmd_ctx, char *cmd, c
 
 	memaccess_tck = swjdp->memaccess_tck;
 	if (argc > 0)
-	{	
+	{
 		memaccess_tck = strtoul(args[0], NULL, 0);
 	}
 
@@ -816,10 +816,10 @@ int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char *
 
 	apsel =  swjdp->apsel;
 	if (argc > 0)
-	{	
+	{
 		apsel = strtoul(args[0], NULL, 0);
 	}
-	
+
 	retval = dap_info_command(cmd_ctx, swjdp, apsel);
 
 	return retval;
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 3204d35a..ec90b715 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -55,7 +55,7 @@ extern char* armv7m_exception_strings[];
 extern char *armv7m_exception_string(int number);
 
 /* offsets into armv7m core register cache */
-enum 
+enum
 {
 	ARMV7M_PC = 15,
 	ARMV7M_xPSR = 16,
@@ -78,18 +78,18 @@ typedef struct armv7m_common_s
 	int exception_number;
 	swjdp_common_t swjdp_info;
 
-	
+
 	/* Direct processor core register read and writes */
 	int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
 	int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
 	/* register cache to processor synchronization */
 	int (*read_core_reg)(struct target_s *target, int num);
 	int (*write_core_reg)(struct target_s *target, int num);
-	
+
 	int (*examine_debug_reason)(target_t *target);
 	void (*pre_debug_entry)(target_t *target);
 	void (*post_debug_entry)(target_t *target);
-	
+
 	void (*pre_restore_context)(target_t *target);
 	void (*post_restore_context)(target_t *target);
 
@@ -99,7 +99,7 @@ typedef struct armv7m_common_s
 typedef struct armv7m_algorithm_s
 {
 	int common_magic;
-	
+
 	enum armv7m_mode core_mode;
 } armv7m_algorithm_t;
 
@@ -133,28 +133,28 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
 
 /* Thumb mode instructions
  */
- 
+
 /* Move to Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
  * Rd: destination register
  * SYSm: source special register
  */
-#define ARMV7M_T_MRS(Rd, SYSm)	((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) 
+#define ARMV7M_T_MRS(Rd, SYSm)	((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
 
 /* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
  * Rd: source register
  * SYSm: destination special register
  */
-#define ARMV7M_T_MSR(SYSm, Rn)	((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16)) 
+#define ARMV7M_T_MSR(SYSm, Rn)	((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
 
-/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK 
+/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
  * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
  * Rd: source register
- * IF: 
+ * IF:
  */
 #define I_FLAG 2
-#define F_FLAG 1  
-#define ARMV7M_T_CPSID(IF)	((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16)) 
-#define ARMV7M_T_CPSIE(IF)	((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16)) 
+#define F_FLAG 1
+#define ARMV7M_T_CPSID(IF)	((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
+#define ARMV7M_T_CPSIE(IF)	((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
 
 /* Breakpoint (Thumb mode) v5 onwards
  * Im: immediate value used by debugger
@@ -178,12 +178,12 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
  * List: for each bit in list: store register
  */
 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
- 
+
 /* Load register with PC relative addressing
  * Rd: register to load
  */
-#define ARMV7M_T_LDR_PCREL(Rd)	((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16)) 
- 
+#define ARMV7M_T_LDR_PCREL(Rd)	((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
+
 /* Move hi register (Thumb mode)
  * Rd: destination register
  * Rm: source register
diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index 60f4805a..c8cd1c3b 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -44,7 +44,7 @@ int breakpoint_add(target_t *target, uint32_t address, uint32_t length, enum bre
 	breakpoint_t *breakpoint = target->breakpoints;
 	breakpoint_t **breakpoint_p = &target->breakpoints;
 	int retval;
-	
+
 	while (breakpoint)
 	{
 		if (breakpoint->address == address)
@@ -52,7 +52,7 @@ int breakpoint_add(target_t *target, uint32_t address, uint32_t length, enum bre
 		breakpoint_p = &breakpoint->next;
 		breakpoint = breakpoint->next;
 	}
-		
+
 	(*breakpoint_p) = malloc(sizeof(breakpoint_t));
 	(*breakpoint_p)->address = address;
 	(*breakpoint_p)->length = length;
@@ -60,7 +60,7 @@ int breakpoint_add(target_t *target, uint32_t address, uint32_t length, enum bre
 	(*breakpoint_p)->set = 0;
 	(*breakpoint_p)->orig_instr = malloc(length);
 	(*breakpoint_p)->next = NULL;
-	
+
 	if ((retval = target_add_breakpoint(target, *breakpoint_p)) != ERROR_OK)
 	{
 		switch (retval)
@@ -83,11 +83,11 @@ int breakpoint_add(target_t *target, uint32_t address, uint32_t length, enum bre
 				break;
 		}
 	}
-	
-	LOG_DEBUG("added %s breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x", 
+
+	LOG_DEBUG("added %s breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x",
 		breakpoint_type_strings[(*breakpoint_p)->type],
 		(*breakpoint_p)->address, (*breakpoint_p)->length);
-	
+
 	return ERROR_OK;
 }
 
@@ -96,7 +96,7 @@ static void breakpoint_free(target_t *target, breakpoint_t *breakpoint_remove)
 {
 	breakpoint_t *breakpoint = target->breakpoints;
 	breakpoint_t **breakpoint_p = &target->breakpoints;
-	
+
 	while (breakpoint)
 	{
 		if (breakpoint == breakpoint_remove)
@@ -104,12 +104,12 @@ static void breakpoint_free(target_t *target, breakpoint_t *breakpoint_remove)
 		breakpoint_p = &breakpoint->next;
 		breakpoint = breakpoint->next;
 	}
-	
+
 	if (breakpoint == NULL)
 		return;
-	
+
 	target_remove_breakpoint(target, breakpoint);
-	
+
 	(*breakpoint_p) = breakpoint->next;
 	free(breakpoint->orig_instr);
 	free(breakpoint);
@@ -119,7 +119,7 @@ void breakpoint_remove(target_t *target, uint32_t address)
 {
 	breakpoint_t *breakpoint = target->breakpoints;
 	breakpoint_t **breakpoint_p = &target->breakpoints;
-	
+
 	while (breakpoint)
 	{
 		if (breakpoint->address == address)
@@ -127,7 +127,7 @@ void breakpoint_remove(target_t *target, uint32_t address)
 		breakpoint_p = &breakpoint->next;
 		breakpoint = breakpoint->next;
 	}
-	
+
 	if (breakpoint)
 	{
 		breakpoint_free(target, breakpoint);
@@ -150,14 +150,14 @@ void breakpoint_clear_target(target_t *target)
 breakpoint_t* breakpoint_find(target_t *target, uint32_t address)
 {
 	breakpoint_t *breakpoint = target->breakpoints;
-	
+
 	while (breakpoint)
 	{
 		if (breakpoint->address == address)
 			return breakpoint;
 		breakpoint = breakpoint->next;
 	}
-	
+
 	return NULL;
 }
 
@@ -166,7 +166,7 @@ int watchpoint_add(target_t *target, uint32_t address, uint32_t length, enum wat
 	watchpoint_t *watchpoint = target->watchpoints;
 	watchpoint_t **watchpoint_p = &target->watchpoints;
 	int retval;
-		
+
 	while (watchpoint)
 	{
 		if (watchpoint->address == address)
@@ -174,7 +174,7 @@ int watchpoint_add(target_t *target, uint32_t address, uint32_t length, enum wat
 		watchpoint_p = &watchpoint->next;
 		watchpoint = watchpoint->next;
 	}
-	
+
 	(*watchpoint_p) = malloc(sizeof(watchpoint_t));
 	(*watchpoint_p)->address = address;
 	(*watchpoint_p)->length = length;
@@ -183,7 +183,7 @@ int watchpoint_add(target_t *target, uint32_t address, uint32_t length, enum wat
 	(*watchpoint_p)->rw = rw;
 	(*watchpoint_p)->set = 0;
 	(*watchpoint_p)->next = NULL;
-		
+
 	if ((retval = target_add_watchpoint(target, *watchpoint_p)) != ERROR_OK)
 	{
 		switch (retval)
@@ -206,11 +206,11 @@ int watchpoint_add(target_t *target, uint32_t address, uint32_t length, enum wat
 				break;
 		}
 	}
-	
+
 	LOG_DEBUG("added %s watchpoint at 0x%8.8" PRIx32 " of length 0x%8.8x",
 		watchpoint_rw_strings[(*watchpoint_p)->rw],
 		(*watchpoint_p)->address, (*watchpoint_p)->length);
-	
+
 	return ERROR_OK;
 }
 
@@ -226,7 +226,7 @@ static void watchpoint_free(target_t *target, watchpoint_t *watchpoint_remove)
 		watchpoint_p = &watchpoint->next;
 		watchpoint = watchpoint->next;
 	}
-	
+
 	if (watchpoint == NULL)
 		return;
 	target_remove_watchpoint(target, watchpoint);
@@ -238,7 +238,7 @@ void watchpoint_remove(target_t *target, uint32_t address)
 {
 	watchpoint_t *watchpoint = target->watchpoints;
 	watchpoint_t **watchpoint_p = &target->watchpoints;
-	
+
 	while (watchpoint)
 	{
 		if (watchpoint->address == address)
@@ -246,7 +246,7 @@ void watchpoint_remove(target_t *target, uint32_t address)
 		watchpoint_p = &watchpoint->next;
 		watchpoint = watchpoint->next;
 	}
-	
+
 	if (watchpoint)
 	{
 		watchpoint_free(target, watchpoint);
diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index 70605469..e6714d00 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -44,7 +44,7 @@ extern char* cortex_m3_state_strings[];
 #define DCB_DCRDR	0xE000EDF8
 #define DCB_DEMCR	0xE000EDFC
 
-#define DCRSR_WnR	(1 << 16)	
+#define DCRSR_WnR	(1 << 16)
 
 #define DWT_CTRL	0xE0001000
 #define DWT_COMP0	0xE0001020
@@ -138,12 +138,12 @@ typedef struct cortex_m3_common_s
 {
 	int common_magic;
 	arm_jtag_t jtag_info;
-	
+
 	/* Context information */
 	uint32_t dcb_dhcsr;
 	uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
 	uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
-	
+
 	/* Flash Patch and Breakpoint (FPB) */
 	int fp_num_lit;
 	int fp_num_code;
@@ -151,16 +151,16 @@ typedef struct cortex_m3_common_s
 	int fpb_enabled;
 	int auto_bp_type;
 	cortex_m3_fp_comparator_t *fp_comparator_list;
-	
+
 	/* Data Watchpoint and Trace (DWT) */
 	int dwt_num_comp;
 	int dwt_comp_available;
 	cortex_m3_dwt_comparator_t *dwt_comparator_list;
-	
+
 	/* Interrupts */
 	int intlinesnum;
 	uint32_t *intsetenable;
-	
+
 	armv7m_common_t armv7m;
 //	swjdp_common_t swjdp_info;
 	void *arch_info;
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index b9339bf3..fab9949d 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -132,32 +132,32 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr)
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = out_buf;
-	
+
 	fields[0].in_value = NULL;
-	
-	
-	
-	
+
+
+
+
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 3;
 	fields[1].out_value = &sysspeed_buf;
-	
+
 	fields[1].in_value = NULL;
-	
-	
-	
-	
+
+
+
+
 
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 32;
 	fields[2].out_value = instr_buf;
-	
+
 	fields[2].in_value = NULL;
-	
-	
-	
-	
+
+
+
+
 
 	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 72b43149..f0ec6e4b 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -38,7 +38,7 @@ char* mips32_core_reg_list[] =
 	"status", "lo", "hi", "badvaddr", "cause", "pc"
 };
 
-mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = 
+mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
 {
 	{0, NULL, NULL},
 	{1, NULL, NULL},
@@ -72,7 +72,7 @@ mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
 	{29, NULL, NULL},
 	{30, NULL, NULL},
 	{31, NULL, NULL},
-	
+
 	{32, NULL, NULL},
 	{33, NULL, NULL},
 	{34, NULL, NULL},
@@ -101,14 +101,14 @@ int mips32_get_core_reg(reg_t *reg)
 	mips32_core_reg_t *mips32_reg = reg->arch_info;
 	target_t *target = mips32_reg->target;
 	mips32_common_t *mips32_target = target->arch_info;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
 	retval = mips32_target->read_core_reg(target, mips32_reg->num);
-	
+
 	return retval;
 }
 
@@ -117,12 +117,12 @@ int mips32_set_core_reg(reg_t *reg, uint8_t *buf)
 	mips32_core_reg_t *mips32_reg = reg->arch_info;
 	target_t *target = mips32_reg->target;
 	uint32_t value = buf_get_u32(buf, 0, 32);
-		
+
 	if (target->state != TARGET_HALTED)
 	{
 		return ERROR_TARGET_NOT_HALTED;
 	}
-		
+
 	buf_set_u32(reg->value, 0, 32, value);
 	reg->dirty = 1;
 	reg->valid = 1;
@@ -134,10 +134,10 @@ int mips32_read_core_reg(struct target_s *target, int num)
 {
 	uint32_t reg_value;
 	mips32_core_reg_t *mips_core_reg;
-	
+
 	/* get pointers to arch-specific information */
 	mips32_common_t *mips32 = target->arch_info;
-		
+
 	if ((num < 0) || (num >= MIPS32NUMCOREREGS))
 		return ERROR_INVALID_ARGUMENTS;
 
@@ -146,28 +146,28 @@ int mips32_read_core_reg(struct target_s *target, int num)
 	buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
 	mips32->core_cache->reg_list[num].valid = 1;
 	mips32->core_cache->reg_list[num].dirty = 0;
-	
-	return ERROR_OK;	
+
+	return ERROR_OK;
 }
 
 int mips32_write_core_reg(struct target_s *target, int num)
 {
 	uint32_t reg_value;
 	mips32_core_reg_t *mips_core_reg;
-	
+
 	/* get pointers to arch-specific information */
 	mips32_common_t *mips32 = target->arch_info;
 
 	if ((num < 0) || (num >= MIPS32NUMCOREREGS))
 		return ERROR_INVALID_ARGUMENTS;
-	
+
 	reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
 	mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
 	mips32->core_regs[num] = reg_value;
 	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 	mips32->core_cache->reg_list[num].valid = 1;
 	mips32->core_cache->reg_list[num].dirty = 0;
-	
+
 	return ERROR_OK;
 }
 
@@ -176,13 +176,13 @@ int mips32_invalidate_core_regs(target_t *target)
 	/* get pointers to arch-specific information */
 	mips32_common_t *mips32 = target->arch_info;
 	int i;
-	
+
 	for (i = 0; i < mips32->core_cache->num_regs; i++)
 	{
 		mips32->core_cache->reg_list[i].valid = 0;
 		mips32->core_cache->reg_list[i].dirty = 0;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -191,16 +191,16 @@ int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
 	/* get pointers to arch-specific information */
 	mips32_common_t *mips32 = target->arch_info;
 	int i;
-	
+
 	/* include floating point registers */
 	*reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
 	*reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
-	
+
 	for (i = 0; i < MIPS32NUMCOREREGS; i++)
 	{
 		(*reg_list)[i] = &mips32->core_cache->reg_list[i];
 	}
-	
+
 	/* add dummy floating points regs */
 	for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
 	{
@@ -213,14 +213,14 @@ int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
 int mips32_save_context(target_t *target)
 {
 	int i;
-	
+
 	/* get pointers to arch-specific information */
 	mips32_common_t *mips32 = target->arch_info;
 	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-	
+
 	/* read core registers */
 	mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
-	
+
 	for (i = 0; i < MIPS32NUMCOREREGS; i++)
 	{
 		if (!mips32->core_cache->reg_list[i].valid)
@@ -228,18 +228,18 @@ int mips32_save_context(target_t *target)
 			mips32->read_core_reg(target, i);
 		}
 	}
-	
-	return ERROR_OK;		
+
+	return ERROR_OK;
 }
 
 int mips32_restore_context(target_t *target)
 {
 	int i;
-	
+
 	/* get pointers to arch-specific information */
 	mips32_common_t *mips32 = target->arch_info;
 	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-	
+
 	for (i = 0; i < MIPS32NUMCOREREGS; i++)
 	{
 		if (mips32->core_cache->reg_list[i].dirty)
@@ -247,27 +247,27 @@ int mips32_restore_context(target_t *target)
 			mips32->write_core_reg(target, i);
 		}
 	}
-	
+
 	/* write core regs */
 	mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
-	
-	return ERROR_OK;		
+
+	return ERROR_OK;
 }
 
 int mips32_arch_state(struct target_s *target)
 {
 	mips32_common_t *mips32 = target->arch_info;
-	
+
 	if (mips32->common_magic != MIPS32_COMMON_MAGIC)
 	{
 		LOG_ERROR("BUG: called for a non-MIPS32 target");
 		exit(-1);
 	}
-	
+
 	LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
 		Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 		buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
-	
+
 	return ERROR_OK;
 }
 
@@ -282,20 +282,20 @@ reg_cache_t *mips32_build_reg_cache(target_t *target)
 	reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 	mips32_core_reg_t *arch_info = malloc(sizeof(mips32_core_reg_t) * num_regs);
 	int i;
-	
+
 	if (mips32_core_reg_arch_type == -1)
 		mips32_core_reg_arch_type = register_reg_arch_type(mips32_get_core_reg, mips32_set_core_reg);
 
 	register_init_dummy(&mips32_gdb_dummy_fp_reg);
 
-	/* Build the process context cache */ 
+	/* Build the process context cache */
 	cache->name = "mips32 registers";
 	cache->next = NULL;
 	cache->reg_list = reg_list;
 	cache->num_regs = num_regs;
 	(*cache_p) = cache;
 	mips32->core_cache = cache;
-	
+
 	for (i = 0; i < num_regs; i++)
 	{
 		arch_info[i] = mips32_core_reg_list_arch_info[i];
@@ -311,7 +311,7 @@ reg_cache_t *mips32_build_reg_cache(target_t *target)
 		reg_list[i].arch_type = mips32_core_reg_arch_type;
 		reg_list[i].arch_info = &arch_info[i];
 	}
-	
+
 	return cache;
 }
 
@@ -319,15 +319,15 @@ int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t
 {
 	target->arch_info = mips32;
 	mips32->common_magic = MIPS32_COMMON_MAGIC;
-	
+
 	/* has breakpoint/watchpint unit been scanned */
 	mips32->bp_scanned = 0;
 	mips32->data_break_list = NULL;
-	
+
 	mips32->ejtag_info.tap = tap;
 	mips32->read_core_reg = mips32_read_core_reg;
 	mips32->write_core_reg = mips32_write_core_reg;
-	
+
 	return ERROR_OK;
 }
 
@@ -345,11 +345,11 @@ int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
 int mips32_examine(struct target_s *target)
 {
 	mips32_common_t *mips32 = target->arch_info;
-	
+
 	if (!target_was_examined(target))
 	{
 		target_set_examined(target);
-	
+
 		/* we will configure later */
 		mips32->bp_scanned = 0;
 		mips32->num_inst_bpoints = 0;
@@ -357,7 +357,7 @@ int mips32_examine(struct target_s *target)
 		mips32->num_inst_bpoints_avail = 0;
 		mips32->num_data_bpoints_avail = 0;
 	}
-		
+
 	return ERROR_OK;
 }
 
@@ -368,20 +368,20 @@ int mips32_configure_break_unit(struct target_s *target)
 	int retval;
 	uint32_t dcr, bpinfo;
 	int i;
-	
+
 	if (mips32->bp_scanned)
 		return ERROR_OK;
-	
+
 	/* get info about breakpoint support */
 	if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
 		return retval;
-	
+
 	if (dcr & (1 << 16))
 	{
 		/* get number of inst breakpoints */
 		if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
 			return retval;
-		
+
 		mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
 		mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
 		mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(mips32_comparator_t));
@@ -389,18 +389,18 @@ int mips32_configure_break_unit(struct target_s *target)
 		{
 			mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
 		}
-		
+
 		/* clear IBIS reg */
 		if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
 			return retval;
 	}
-	
+
 	if (dcr & (1 << 17))
 	{
 		/* get number of data breakpoints */
 		if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
 			return retval;
-		
+
 		mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
 		mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
 		mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(mips32_comparator_t));
@@ -408,16 +408,16 @@ int mips32_configure_break_unit(struct target_s *target)
 		{
 			mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
 		}
-		
+
 		/* clear DBIS reg */
 		if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
 			return retval;
 	}
-	
+
 	LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
-	
+
 	mips32->bp_scanned = 1;
-	
+
 	return ERROR_OK;
 }
 
@@ -426,11 +426,11 @@ int mips32_enable_interrupts(struct target_s *target, int enable)
 	int retval;
 	int update = 0;
 	uint32_t dcr;
-	
+
 	/* read debug control register */
 	if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
 		return retval;
-	
+
 	if (enable)
 	{
 		if (!(dcr & (1 << 4)))
@@ -449,12 +449,12 @@ int mips32_enable_interrupts(struct target_s *target, int enable)
 			update = 1;
 		}
 	}
-	
+
 	if (update)
 	{
 		if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
 			return retval;
 	}
-	
+
 	return ERROR_OK;
 }
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 33f0c833..bc88bc37 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -31,7 +31,7 @@
 #define MIPS32_COMMON_MAGIC		0xB320B320
 
 /* offsets into mips32 core register cache */
-enum 
+enum
 {
 	MIPS32_PC = 37,
 	MIPS32NUMCOREREGS
@@ -52,7 +52,7 @@ typedef struct mips32_common_s
 	reg_cache_t *core_cache;
 	mips_ejtag_t ejtag_info;
 	uint32_t core_regs[MIPS32NUMCOREREGS];
-	
+
 	int bp_scanned;
 	int num_inst_bpoints;
 	int num_data_bpoints;
@@ -60,7 +60,7 @@ typedef struct mips32_common_s
 	int num_data_bpoints_avail;
 	mips32_comparator_t *inst_break_list;
 	mips32_comparator_t *data_break_list;
-	
+
 	/* register cache to processor synchronization */
 	int (*read_core_reg)(struct target_s *target, int num);
 	int (*write_core_reg)(struct target_s *target, int num);
diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c
index e67c4ce7..9a380841 100644
--- a/src/target/mips32_dmaacc.c
+++ b/src/target/mips32_dmaacc.c
@@ -191,7 +191,7 @@ begin_ejtag_dma_read_b:
 		case 2:
 			*data = (v >> 16) & 0xff;
 			break;
-		case 3: 
+		case 3:
 			*data = (v >> 24) & 0xff;
 			break;
 	}
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index c498aff9..0d33f391 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -26,7 +26,7 @@ This version has optimized assembly routines for 32 bit operations:
 - write word
 - write array of words
 
-One thing to be aware of is that the MIPS32 cpu will execute the 
+One thing to be aware of is that the MIPS32 cpu will execute the
 instruction after a branch instruction (one delay slot).
 
 For example:
@@ -36,7 +36,7 @@ For example:
     B foo
     LW $1, ($2 +100)
 
-The LW $1, ($2 +100) instruction is also executed. If this is 
+The LW $1, ($2 +100) instruction is also executed. If this is
 not wanted a NOP can be inserted:
 
     LW $2, ($5 +10)
@@ -92,8 +92,8 @@ typedef struct {
 static int wait_for_pracc_rw(mips_ejtag_t *ejtag_info, uint32_t *ctrl)
 {
 	uint32_t ejtag_ctrl;
-	
-	while (1) 
+
+	while (1)
 	{
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 		ejtag_ctrl = ejtag_info->ejtag_ctrl;
@@ -103,7 +103,7 @@ static int wait_for_pracc_rw(mips_ejtag_t *ejtag_info, uint32_t *ctrl)
 		LOG_DEBUG("DEBUGMODULE: No memory access in progress!\n");
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
-	
+
 	*ctrl = ejtag_ctrl;
 	return ERROR_OK;
 }
@@ -141,12 +141,12 @@ static int mips32_pracc_exec_read(mips32_pracc_context *ctx, uint32_t address)
 	{
 		/* TODO: send JMP 0xFF200000 instruction. Hopefully processor jump back
 		 * to start of debug vector */
-		
+
 		data = 0;
 		LOG_ERROR("Error reading unexpected address %8.8" PRIx32 "", address);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
-	
+
 	/* Send the data out */
 	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
 	mips_ejtag_drscan_32(ctx->ejtag_info, &data);
@@ -159,7 +159,7 @@ static int mips32_pracc_exec_read(mips32_pracc_context *ctx, uint32_t address)
 
 	jtag_add_clocks(5);
 	jtag_execute_queue();
-	
+
 
 	return ERROR_OK;
 }
@@ -172,7 +172,7 @@ static int mips32_pracc_exec_write(mips32_pracc_context *ctx, uint32_t address)
 
 	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
 	mips_ejtag_drscan_32(ctx->ejtag_info, &data);
-	
+
 	/* Clear access pending bit */
 	ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
 	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
@@ -180,7 +180,7 @@ static int mips32_pracc_exec_write(mips32_pracc_context *ctx, uint32_t address)
 
 	jtag_add_clocks(5);
 	jtag_execute_queue();
-	
+
 	if ((address >= MIPS32_PRACC_PARAM_IN)
 		&& (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4))
 	{
@@ -203,7 +203,7 @@ static int mips32_pracc_exec_write(mips32_pracc_context *ctx, uint32_t address)
 		LOG_ERROR("Error writing unexpected address %8.8" PRIx32 "", address);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -214,7 +214,7 @@ int mips32_pracc_exec(mips_ejtag_t *ejtag_info, int code_len, uint32_t *code, in
 	mips32_pracc_context ctx;
 	int retval;
 	int pass = 0;
-	
+
 	ctx.local_iparam = param_in;
 	ctx.local_oparam = param_out;
 	ctx.num_iparam = num_param_in;
@@ -223,18 +223,18 @@ int mips32_pracc_exec(mips_ejtag_t *ejtag_info, int code_len, uint32_t *code, in
 	ctx.code_len = code_len;
 	ctx.ejtag_info = ejtag_info;
 	ctx.stack_offset = 0;
-	
+
 	while (1)
 	{
 		if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
 			return retval;
-		
+
 		address = data = 0;
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
 		mips_ejtag_drscan_32(ejtag_info, &address);
 
 //		printf("Adres: %.8x\n", address);
-		
+
 		/* Check for read or write */
 		if (ejtag_ctrl & EJTAG_CTRL_PRNW)
 		{
@@ -250,22 +250,22 @@ int mips32_pracc_exec(mips_ejtag_t *ejtag_info, int code_len, uint32_t *code, in
 			{
 				break;
 			}
-			
+
 			if ((retval = mips32_pracc_exec_read(&ctx, address)) != ERROR_OK)
 				return retval;
 
 		}
-		
+
 		if (cycle == 0)
 			break;
 	}
-	
+
 	/* stack sanity check */
 	if (ctx.stack_offset != 0)
 	{
 		LOG_DEBUG("Pracc Stack not zero");
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -283,12 +283,12 @@ int mips32_pracc_read_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int
 			else
 				return mips32_pracc_read_mem32(ejtag_info, addr, count, (uint32_t*)buf);
 	}
-	
+
 	return ERROR_OK;
 }
 
 int mips32_pracc_read_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint32_t *buf)
-{	
+{
 	uint32_t code[] = {
 															/* start: */
 		MIPS32_MTC0(15,31,0),								/* move $15 to COP0 DeSave */
@@ -298,7 +298,7 @@ int mips32_pracc_read_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 		MIPS32_SW(9,0,15), 									/* sw $9,($15) */
 		MIPS32_SW(10,0,15), 								/* sw $10,($15) */
 		MIPS32_SW(11,0,15), 								/* sw $11,($15) */
-			
+
 		MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)),		/* $8 = MIPS32_PRACC_PARAM_IN */
 		MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
 		MIPS32_LW(9,0,8),									/* $9 = mem[$8]; read addr */
@@ -309,14 +309,14 @@ int mips32_pracc_read_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 															/* loop: */
 		MIPS32_BEQ(0,10,9),									/* beq 0, $10, end */
 		MIPS32_NOP,
-		
+
 		MIPS32_LW(8,0,9), 									/* lw $8,0($9), Load $8 with the word @mem[$9] */
 		MIPS32_SW(8,0,11), 									/* sw $8,0($11) */
-		
+
 		MIPS32_ADDI(10,10,NEG16(1)), 						/* $10-- */
 		MIPS32_ADDI(9,9,4), 								/* $1 += 4 */
 		MIPS32_ADDI(11,11,4), 								/* $11 += 4 */
-		
+
 		MIPS32_NOP,
 		MIPS32_B(NEG16(9)),									/* b loop */
 		MIPS32_NOP,
@@ -330,29 +330,29 @@ int mips32_pracc_read_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 		MIPS32_B(NEG16(31)),								/* b start */
 		MIPS32_NOP,
 	};
-	
+
 	int retval = ERROR_OK;
 	int blocksize;
 	int bytesread;
 	uint32_t param_in[2];
-	
+
 	bytesread = 0;
-	
+
 	while (count > 0)
-	{	
+	{
 		blocksize = count;
 		if (count > 0x400)
 			blocksize = 0x400;
-		
+
 		param_in[0] = addr;
 		param_in[1] = blocksize;
-		
-		if ((retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, 
+
+		if ((retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code,
 			sizeof(param_in)/sizeof(param_in[0]), param_in, blocksize, &buf[bytesread], 1)) != ERROR_OK)
 		{
 			return retval;
 		}
-		
+
 		count -= blocksize;
 		addr += blocksize;
 		bytesread += blocksize;
@@ -386,7 +386,7 @@ int mips32_pracc_read_u32(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t *buf
 
 	param_in[0] = addr;
 
-	if ((retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, 
+	if ((retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code,
 		sizeof(param_in)/sizeof(param_in[0]), param_in, sizeof(uint32_t), buf, 1)) != ERROR_OK)
 	{
 		return retval;
@@ -406,7 +406,7 @@ int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 		MIPS32_SW(9,0,15), 									/* sw $9,($15) */
 		MIPS32_SW(10,0,15), 								/* sw $10,($15) */
 		MIPS32_SW(11,0,15), 								/* sw $11,($15) */
-			
+
 		MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)),		/* $8 = MIPS32_PRACC_PARAM_IN */
 		MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
 		MIPS32_LW(9,0,8),									/* $9 = mem[$8]; read addr */
@@ -417,10 +417,10 @@ int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 															/* loop: */
 		MIPS32_BEQ(0,10,9), 								/* beq 0, $10, end */
 		MIPS32_NOP,
-		
+
 		MIPS32_LHU(8,0,9), 									/* lw $8,0($9), Load $8 with the halfword @mem[$9] */
 		MIPS32_SW(8,0,11), 									/* sw $8,0($11) */
-		
+
 		MIPS32_ADDI(10,10,NEG16(1)), 						/* $10-- */
 		MIPS32_ADDI(9,9,2), 								/* $9 += 2 */
 		MIPS32_ADDI(11,11,4), 								/* $11 += 4 */
@@ -441,36 +441,36 @@ int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 //	/* TODO remove array */
 	uint32_t param_out[count];
 	int i;
-	
+
 //	int retval;
 	int blocksize;
 	int bytesread;
 	uint32_t param_in[2];
-	
+
 	bytesread = 0;
-	
+
 	//while (count > 0)
-	{	
+	{
 		blocksize = count;
 		if (count > 0x400)
 			blocksize = 0x400;
-		
+
 		param_in[0] = addr;
 		param_in[1] = blocksize;
-		
+
 		mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
 			sizeof(param_in)/sizeof(param_in[0]), param_in, count, param_out, 1);
-		
+
 //		count -= blocksize;
 //		addr += blocksize;
 //		bytesread += blocksize;
 	}
-	
+
 	for (i = 0; i < count; i++)
 	{
 		buf[i] = param_out[i];
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -485,7 +485,7 @@ int mips32_pracc_read_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count, u
 		MIPS32_SW(9,0,15), 									/* sw $9,($15) */
 		MIPS32_SW(10,0,15), 								/* sw $10,($15) */
 		MIPS32_SW(11,0,15), 								/* sw $11,($15) */
-			
+
 		MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), 		/* $8 = MIPS32_PRACC_PARAM_IN */
 		MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
 		MIPS32_LW(9,0,8), 									/* $9 = mem[$8]; read addr */
@@ -496,10 +496,10 @@ int mips32_pracc_read_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count, u
 															/* loop: */
 		MIPS32_BEQ(0,10,9), 								/* beq 0, $10, end */
 		MIPS32_NOP,
-		
+
 		MIPS32_LBU(8,0,9), 									/* lw $8,0($9), Load t4 with the byte @mem[t1] */
 		MIPS32_SW(8,0,11), 									/* sw $8,0($11) */
-		
+
 		MIPS32_ADDI(10,10,NEG16(1)), 						/* $10-- */
 		MIPS32_ADDI(9,9,1), 								/* $9 += 1 */
 		MIPS32_ADDI(11,11,4), 								/* $11 += 4 */
@@ -516,35 +516,35 @@ int mips32_pracc_read_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count, u
 		MIPS32_B(NEG16(31)),								/* b start */
 		MIPS32_NOP,
 	};
-	
+
 //	/* TODO remove array */
 	uint32_t param_out[count];
 	int i;
-	
+
 //	int retval;
 	int blocksize;
 	int bytesread;
 	uint32_t param_in[2];
-	
+
 	bytesread = 0;
-	
+
 //	while (count > 0)
-	{	
+	{
 		blocksize = count;
 		if (count > 0x400)
 			blocksize = 0x400;
-		
+
 		param_in[0] = addr;
 		param_in[1] = blocksize;
-		
+
 		mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
 			sizeof(param_in)/sizeof(param_in[0]), param_in, count, param_out, 1);
-		
+
 //		count -= blocksize;
 //		addr += blocksize;
 //		bytesread += blocksize;
 	}
-	
+
 	for (i = 0; i < count; i++)
 	{
 		buf[i] = param_out[i];
@@ -567,7 +567,7 @@ int mips32_pracc_write_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, in
 			else
 				return mips32_pracc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf);
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -584,7 +584,7 @@ int mips32_pracc_write_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 		MIPS32_SW(9,0,15), 									/* sw $9,($15) */
 		MIPS32_SW(10,0,15), 								/* sw $10,($15) */
 		MIPS32_SW(11,0,15), 								/* sw $11,($15) */
-		
+
 		MIPS32_ADDI(8,15,NEG16(MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN)),  //$8= MIPS32_PRACC_PARAM_IN
 		MIPS32_LW(9,0,8), 									/* Load write addr to $9 */
 		MIPS32_LW(10,4,8),	//last address 									/* Load write count to $10 */
@@ -593,7 +593,7 @@ int mips32_pracc_write_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 //loop:
 		MIPS32_LW(11,0,8), 									/* lw $11,0($8), Load $11 with the word @mem[$8] */
 		MIPS32_SW(11,0,9), 									/* sw $11,0($9) */
-		
+
 		MIPS32_ADDI(9,9,4), 								/* $9 += 4 */
 		MIPS32_BNE(10,9,NEG16(4)),  //was 9 BNE $10, 9, loop									/* b loop */
 		MIPS32_ADDI(8,8,4),  //this instruction is part of the loop (one delay slot)!	/* $8 += 4 */
@@ -606,14 +606,14 @@ int mips32_pracc_write_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 		MIPS32_MFC0(15,31,0),								/* move COP0 DeSave to $15 */
 		MIPS32_NOP, //this one will not be executed
 	};
-	
+
 	/* TODO remove array */
 	uint32_t param_in[count + 2];
 	param_in[0] = addr;
 	param_in[1] = addr + count * sizeof(uint32_t);	//last address
-    
+
 	memcpy(&param_in[2], buf, count * sizeof(uint32_t));
-	
+
 	mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
 		sizeof(param_in)/sizeof(param_in[0]),param_in, 0, NULL, 1);
 
@@ -629,7 +629,7 @@ int mips32_pracc_write_u32(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t *bu
 		MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
 		MIPS32_SW(8,0,15), 									/* sw $8,($15) */
 		MIPS32_SW(9,0,15), 									/* sw $9,($15) */
-	
+
 		MIPS32_LW(8,NEG16((MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN)-4), 15),  //load R8 @ param_in[1] = data
 		MIPS32_LW(9,NEG16(MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN), 15),  //load R9 @ param_in[0] = address
 
@@ -664,7 +664,7 @@ int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 		MIPS32_SW(9,0,15), 									/* sw $9,($15) */
 		MIPS32_SW(10,0,15), 								/* sw $10,($15) */
 		MIPS32_SW(11,0,15), 								/* sw $11,($15) */
-		
+
 		MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), 		/* $8 = MIPS32_PRACC_PARAM_IN */
 		MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
 		MIPS32_LW(9,0,8), 									/* Load write addr to $9 */
@@ -674,14 +674,14 @@ int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 															/* loop: */
 		MIPS32_BEQ(0,10,9),									/* beq $0, $10, end */
 		MIPS32_NOP,
-		
+
 		MIPS32_LW(11,0,8), 									/* lw $11,0($8), Load $11 with the word @mem[$8] */
 		MIPS32_SH(11,0,9), 									/* sh $11,0($9) */
-		
+
 		MIPS32_ADDI(10,10,NEG16(1)), 						/* $10-- */
 		MIPS32_ADDI(9,9,2), 								/* $9 += 2 */
 		MIPS32_ADDI(8,8,4), 								/* $8 += 4 */
-		
+
 		MIPS32_NOP,
 		MIPS32_B(NEG16(9)),									/* b loop */
 		MIPS32_NOP,
@@ -695,18 +695,18 @@ int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 		MIPS32_B(NEG16(30)),								/* b start */
 		MIPS32_NOP,
 	};
-	
+
 	/* TODO remove array */
 	uint32_t param_in[count + 2];
 	int i;
 	param_in[0] = addr;
 	param_in[1] = count;
-	
+
 	for (i = 0; i < count; i++)
 	{
 		param_in[i + 2] = buf[i];
 	}
-	
+
 	mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
 		sizeof(param_in)/sizeof(param_in[0]), param_in, 0, NULL, 1);
 
@@ -724,7 +724,7 @@ int mips32_pracc_write_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 		MIPS32_SW(9,0,15), 									/* sw $9,($15) */
 		MIPS32_SW(10,0,15), 								/* sw $10,($15) */
 		MIPS32_SW(11,0,15), 								/* sw $11,($15) */
-		
+
 		MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), 		/* $8 = MIPS32_PRACC_PARAM_IN */
 		MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
 		MIPS32_LW(9,0,8), 									/* Load write addr to $9 */
@@ -734,14 +734,14 @@ int mips32_pracc_write_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 															/* loop: */
 		MIPS32_BEQ(0,10,9),									/* beq $0, $10, end */
 		MIPS32_NOP,
-		
+
 		MIPS32_LW(11,0,8), 									/* lw $11,0($8), Load $11 with the word @mem[$8] */
 		MIPS32_SB(11,0,9), 									/* sb $11,0($9) */
-		
+
 		MIPS32_ADDI(10,10,NEG16(1)), 						/* $10-- */
 		MIPS32_ADDI(9,9,1), 								/* $9 += 1 */
 		MIPS32_ADDI(8,8,4), 								/* $8 += 4 */
-		
+
 		MIPS32_NOP,
 		MIPS32_B(NEG16(9)),									/* b loop */
 		MIPS32_NOP,
@@ -755,19 +755,19 @@ int mips32_pracc_write_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count,
 		MIPS32_B(NEG16(30)),								/* b start */
 		MIPS32_NOP,
 	};
-	
+
 	/* TODO remove array */
 	uint32_t param_in[count + 2];
 	int retval;
 	int i;
 	param_in[0] = addr;
 	param_in[1] = count;
-	
+
 	for (i = 0; i < count; i++)
 	{
 		param_in[i + 2] = buf[i];
 	}
-	
+
 	retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
 		sizeof(param_in)/sizeof(param_in[0]), param_in, 0, NULL, 1);
 
@@ -816,7 +816,7 @@ int mips32_pracc_write_regs(mips_ejtag_t *ejtag_info, uint32_t *regs)
 		MIPS32_LW(29,29*4,1), 							/* lw $29,29*4($1) */
 		MIPS32_LW(30,30*4,1), 							/* lw $30,30*4($1) */
 		MIPS32_LW(31,31*4,1), 							/* lw $31,31*4($1) */
-		
+
 		MIPS32_LW(2,32*4,1), 							/* lw $2,32*4($1) */
 		MIPS32_MTC0(2,12,0),							/* move $2 to status */
 		MIPS32_LW(2,33*4,1), 							/* lw $2,33*4($1) */
@@ -829,7 +829,7 @@ int mips32_pracc_write_regs(mips_ejtag_t *ejtag_info, uint32_t *regs)
 		MIPS32_MTC0(2,13,0),							/* move $2 to cause*/
 		MIPS32_LW(2,37*4,1), 							/* lw $2,37*4($1) */
 		MIPS32_MTC0(2,24,0),							/* move $2 to pc */
-		
+
 		MIPS32_LW(2,2*4,1), 							/* lw $2,2*4($1) */
 		MIPS32_LW(1,0,15), 								/* lw $1,($15) */
 		MIPS32_MFC0(15,31,0),							/* move COP0 DeSave to $15 */
@@ -837,12 +837,12 @@ int mips32_pracc_write_regs(mips_ejtag_t *ejtag_info, uint32_t *regs)
 		MIPS32_B(NEG16(55)),							/* b start */
 		MIPS32_NOP,
 	};
-	
+
 	int retval;
-	
+
 	retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
 		38, regs, 0, NULL, 1);
-	
+
 	return retval;
 }
 
@@ -893,7 +893,7 @@ int mips32_pracc_read_regs(mips_ejtag_t *ejtag_info, uint32_t *regs)
 		MIPS32_SW(29,29*4,1), 							/* sw $29,29*4($1) */
 		MIPS32_SW(30,30*4,1), 							/* sw $30,30*4($1) */
 		MIPS32_SW(31,31*4,1), 							/* sw $31,31*4($1) */
-		
+
 		MIPS32_MFC0(2,12,0),							/* move status to $2 */
 		MIPS32_SW(2,32*4,1), 							/* sw $2,32*4($1) */
 		MIPS32_MFLO(2),									/* move lo to $2 */
@@ -906,7 +906,7 @@ int mips32_pracc_read_regs(mips_ejtag_t *ejtag_info, uint32_t *regs)
 		MIPS32_SW(2,36*4,1), 							/* sw $2,36*4($1) */
 		MIPS32_MFC0(2,24,0),							/* move pc to $2 */
 		MIPS32_SW(2,37*4,1), 							/* sw $2,37*4($1) */
-		
+
 		MIPS32_LW(2,0,15), 								/* lw $2,($15) */
 		MIPS32_LW(1,0,15), 								/* lw $1,($15) */
 		MIPS32_MFC0(15,31,0),							/* move COP0 DeSave to $15 */
@@ -914,11 +914,11 @@ int mips32_pracc_read_regs(mips_ejtag_t *ejtag_info, uint32_t *regs)
 		MIPS32_B(NEG16(60)),							/* b start */
 		MIPS32_NOP,
 	};
-	
+
 	int retval;
-	
+
 	retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
 		0, NULL, 38, regs, 1);
-	
+
 	return retval;
 }
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 7d643535..ba66620a 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -46,10 +46,10 @@ int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, void *delete_m
 		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
 
 		field.in_value = NULL;
-		
-		
-		
-		
+
+
+
+
 		jtag_add_ir_scan(1, &field, jtag_get_end_state());
 	}
 
@@ -69,10 +69,10 @@ int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, uint32_t *idcode)
 	field.out_value = NULL;
 
 	field.in_value = (void*)idcode;
-	
-	
-	
-	
+
+
+
+
 	jtag_add_dr_scan(1, &field, jtag_get_end_state());
 
 	if (jtag_execute_queue() != ERROR_OK)
@@ -96,10 +96,10 @@ int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, uint32_t *impcode)
 	field.out_value = NULL;
 
 	field.in_value = (void*)impcode;
-	
-	
-	
-	
+
+
+
+
 	jtag_add_dr_scan(1, &field, jtag_get_end_state());
 
 	if (jtag_execute_queue() != ERROR_OK)
@@ -127,10 +127,10 @@ int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, uint32_t *data)
 	buf_set_u32(field.out_value, 0, field.num_bits, *data);
 
 	field.in_value = r;
-	
-	
-	
-	
+
+
+
+
 	jtag_add_dr_scan(1, &field, jtag_get_end_state());
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -222,7 +222,7 @@ int mips_ejtag_exit_debug(mips_ejtag_t *ejtag_info)
 {
 	uint32_t inst;
 	inst = MIPS32_DRET;
-	
+
 	/* execute our dret instruction */
 	mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
 
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index aac95bbc..5a3fe1cf 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -348,7 +348,7 @@ int mips_m4k_single_step_core(target_t *target)
 
 	/* disable interrupts while stepping */
 	mips32_enable_interrupts(target, 0);
-	
+
 	/* exit debug mode */
 	mips_ejtag_exit_debug(ejtag_info);
 
@@ -404,7 +404,7 @@ int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int
 
 	/* enable interrupts if we are running */
 	mips32_enable_interrupts(target, !debug_execution);
-	
+
 	/* exit debug mode */
 	mips_ejtag_exit_debug(ejtag_info);
 	target->debug_reason = DBG_REASON_NOTHALTED;
@@ -462,7 +462,7 @@ int mips_m4k_step(struct target_s *target, int current, uint32_t address, int ha
 
 	/* disable interrupts while stepping */
 	mips32_enable_interrupts(target, 0);
-		
+
 	/* exit debug mode */
 	mips_ejtag_exit_debug(ejtag_info);
 
@@ -498,7 +498,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 	mips32_common_t *mips32 = target->arch_info;
 	mips32_comparator_t * comparator_list = mips32->inst_break_list;
 	int retval;
-	
+
 	if (breakpoint->set)
 	{
 		LOG_WARNING("breakpoint already set");
@@ -530,7 +530,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		if (breakpoint->length == 4)
 		{
 			uint32_t verify = 0xffffffff;
-			
+
 			if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
 			{
 				return retval;
@@ -539,7 +539,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			{
 				return retval;
 			}
-			
+
 			if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
 			{
 				return retval;
@@ -553,7 +553,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		else
 		{
 			uint16_t verify = 0xffff;
-			
+
 			if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
 			{
 				return retval;
@@ -562,7 +562,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			{
 				return retval;
 			}
-			
+
 			if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
 			{
 				return retval;
@@ -573,7 +573,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 				return ERROR_OK;
 			}
 		}
-		
+
 		breakpoint->set = 20; /* Any nice value but 0 */
 	}
 
@@ -586,7 +586,7 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 	mips32_common_t *mips32 = target->arch_info;
 	mips32_comparator_t * comparator_list = mips32->inst_break_list;
 	int retval;
-	
+
 	if (!breakpoint->set)
 	{
 		LOG_WARNING("breakpoint not set");
@@ -611,7 +611,7 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		if (breakpoint->length == 4)
 		{
 			uint32_t current_instr;
-			
+
 			/* check that user program has not modified breakpoint instruction */
 			if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
 			{
@@ -628,13 +628,13 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		else
 		{
 			uint16_t current_instr;
-			
+
 			/* check that user program has not modified breakpoint instruction */
 			if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
 			{
 				return retval;
 			}
-			
+
 			if (current_instr == MIPS16_SDBBP)
 			{
 				if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
@@ -660,9 +660,9 @@ int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			LOG_INFO("no hardware breakpoint available");
 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
-		
+
 		mips32->num_inst_bpoints_avail--;
-	}	
+	}
 
 	mips_m4k_set_breakpoint(target, breakpoint);
 
@@ -758,7 +758,7 @@ int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t siz
 		return retval;
 
 	/* TAP data register is loaded LSB first (little endian) */
-	if (target->endianness == TARGET_BIG_ENDIAN) 
+	if (target->endianness == TARGET_BIG_ENDIAN)
 	{
 		uint32_t i, t32;
 		uint16_t t16;
@@ -810,7 +810,7 @@ int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t si
 
 		for (i = 0; i < (count*size); i += size)
 		{
-			switch (size) 
+			switch (size)
 			{
 				case 4:
 					t32 = be_to_h_u32(&buffer[i]);
@@ -822,7 +822,7 @@ int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t si
 					break;
 			}
 		}
-	}	   
+	}
 
 	/* if noDMA off, use DMAACC mode for memory write */
 	if (ejtag_info->impcode & EJTAG_IMP_NODMA)
@@ -884,7 +884,7 @@ int mips_m4k_examine(struct target_s *target)
 	{
 		mips_ejtag_get_idcode(ejtag_info, &idcode);
 		ejtag_info->idcode = idcode;
-		
+
 		if (((idcode >> 1) & 0x7FF) == 0x29)
 		{
 			/* we are using a pic32mx so select ejtag port
diff --git a/src/target/target.c b/src/target/target.c
index 67bbcfc1..f95e360f 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -969,7 +969,7 @@ int target_alloc_working_area(struct target_s *target, uint32_t size, working_ar
 
 		if (free_size < size)
 		{
-			LOG_WARNING("not enough working area available(requested %u, free %u)", 
+			LOG_WARNING("not enough working area available(requested %u, free %u)",
 				    (unsigned)(size), (unsigned)(free_size));
 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
@@ -1102,7 +1102,7 @@ int target_arch_state(struct target_s *target)
 int target_write_buffer(struct target_s *target, uint32_t address, uint32_t size, uint8_t *buffer)
 {
 	int retval;
-	LOG_DEBUG("writing buffer of %i byte at 0x%8.8x", 
+	LOG_DEBUG("writing buffer of %i byte at 0x%8.8x",
 		  (int)size, (unsigned)address);
 
 	if (!target_was_examined(target))
@@ -1118,8 +1118,8 @@ int target_write_buffer(struct target_s *target, uint32_t address, uint32_t size
 	if ((address + size - 1) < address)
 	{
 		/* GDB can request this when e.g. PC is 0xfffffffc*/
-		LOG_ERROR("address + size wrapped(0x%08x, 0x%08x)", 
-				  (unsigned)address, 
+		LOG_ERROR("address + size wrapped(0x%08x, 0x%08x)",
+				  (unsigned)address,
 				  (unsigned)size);
 		return ERROR_FAIL;
 	}
@@ -1184,7 +1184,7 @@ int target_write_buffer(struct target_s *target, uint32_t address, uint32_t size
 int target_read_buffer(struct target_s *target, uint32_t address, uint32_t size, uint8_t *buffer)
 {
 	int retval;
-	LOG_DEBUG("reading buffer of %i byte at 0x%8.8x", 
+	LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
 			  (int)size, (unsigned)address);
 
 	if (!target_was_examined(target))
@@ -1200,8 +1200,8 @@ int target_read_buffer(struct target_s *target, uint32_t address, uint32_t size,
 	if ((address + size - 1) < address)
 	{
 		/* GDB can request this when e.g. PC is 0xfffffffc*/
-		LOG_ERROR("address + size wrapped(0x%08" PRIx32 ", 0x%08" PRIx32 ")", 
-				  address, 
+		LOG_ERROR("address + size wrapped(0x%08" PRIx32 ", 0x%08" PRIx32 ")",
+				  address,
 				  size);
 		return ERROR_FAIL;
 	}
@@ -1326,14 +1326,14 @@ int target_read_u32(struct target_s *target, uint32_t address, uint32_t *value)
 	if (retval == ERROR_OK)
 	{
 		*value = target_buffer_get_u32(target, value_buf);
-		LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8" PRIx32 "", 
-				  address, 
+		LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8" PRIx32 "",
+				  address,
 				  *value);
 	}
 	else
 	{
 		*value = 0x0;
-		LOG_DEBUG("address: 0x%8.8" PRIx32 " failed", 
+		LOG_DEBUG("address: 0x%8.8" PRIx32 " failed",
 				  address);
 	}
 
@@ -1354,14 +1354,14 @@ int target_read_u16(struct target_s *target, uint32_t address, uint16_t *value)
 	if (retval == ERROR_OK)
 	{
 		*value = target_buffer_get_u16(target, value_buf);
-		LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%4.4x", 
-				  address, 
+		LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%4.4x",
+				  address,
 				  *value);
 	}
 	else
 	{
 		*value = 0x0;
-		LOG_DEBUG("address: 0x%8.8" PRIx32 " failed", 
+		LOG_DEBUG("address: 0x%8.8" PRIx32 " failed",
 				  address);
 	}
 
@@ -1379,14 +1379,14 @@ int target_read_u8(struct target_s *target, uint32_t address, uint8_t *value)
 
 	if (retval == ERROR_OK)
 	{
-		LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%2.2x", 
-				  address, 
+		LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%2.2x",
+				  address,
 				  *value);
 	}
 	else
 	{
 		*value = 0x0;
-		LOG_DEBUG("address: 0x%8.8" PRIx32 " failed", 
+		LOG_DEBUG("address: 0x%8.8" PRIx32 " failed",
 				  address);
 	}
 
@@ -1403,8 +1403,8 @@ int target_write_u32(struct target_s *target, uint32_t address, uint32_t value)
 		return ERROR_FAIL;
 	}
 
-	LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8" PRIx32 "", 
-			  address, 
+	LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8" PRIx32 "",
+			  address,
 			  value);
 
 	target_buffer_set_u32(target, value_buf, value);
@@ -1426,8 +1426,8 @@ int target_write_u16(struct target_s *target, uint32_t address, uint16_t value)
 		return ERROR_FAIL;
 	}
 
-	LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8x", 
-			  address, 
+	LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8x",
+			  address,
 			  value);
 
 	target_buffer_set_u16(target, value_buf, value);
@@ -1448,7 +1448,7 @@ int target_write_u8(struct target_s *target, uint32_t address, uint8_t value)
 		return ERROR_FAIL;
 	}
 
-	LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%2.2x", 
+	LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%2.2x",
 			  address, value);
 
 	if ((retval = target_write_memory(target, address, 1, 1, &value)) != ERROR_OK)
@@ -1734,12 +1734,12 @@ static int handle_reg_command(struct command_context_s *cmd_ctx, char *cmd, char
 			for (i = 0; i < cache->num_regs; i++)
 			{
 				value = buf_to_str(cache->reg_list[i].value, cache->reg_list[i].size, 16);
-				command_print(cmd_ctx, "(%i) %s (/%i): 0x%s (dirty: %i, valid: %i)", 
-							  count++, 
-							  cache->reg_list[i].name, 
+				command_print(cmd_ctx, "(%i) %s (/%i): 0x%s (dirty: %i, valid: %i)",
+							  count++,
+							  cache->reg_list[i].name,
 							  (int)(cache->reg_list[i].size),
-							  value, 
-							  cache->reg_list[i].dirty, 
+							  value,
+							  cache->reg_list[i].dirty,
 							  cache->reg_list[i].valid);
 				free(value);
 			}
@@ -2066,7 +2066,7 @@ static void handle_md_output(struct command_context_s *cmd_ctx,
 		{
 			output_len += snprintf(output + output_len,
 					sizeof(output) - output_len,
-					"0x%8.8x: ", 
+					"0x%8.8x: ",
 					(unsigned)(address + (i*size)));
 		}
 
@@ -2241,7 +2241,7 @@ static int handle_load_image_command(struct command_context_s *cmd_ctx, char *cm
 
 	duration_t duration;
 	char *duration_text;
-	
+
 	int retval = parse_load_image_command_args(args, argc,
 			&image, &min_address, &max_address);
 	if (ERROR_OK != retval)
@@ -2262,8 +2262,8 @@ static int handle_load_image_command(struct command_context_s *cmd_ctx, char *cm
 		buffer = malloc(image.sections[i].size);
 		if (buffer == NULL)
 		{
-			command_print(cmd_ctx, 
-						  "error allocating buffer for section (%d bytes)", 
+			command_print(cmd_ctx,
+						  "error allocating buffer for section (%d bytes)",
 						  (int)(image.sections[i].size));
 			break;
 		}
@@ -2300,8 +2300,8 @@ static int handle_load_image_command(struct command_context_s *cmd_ctx, char *cm
 				break;
 			}
 			image_size += length;
-			command_print(cmd_ctx, "%u byte written at address 0x%8.8" PRIx32 "", 
-						  (unsigned int)length, 
+			command_print(cmd_ctx, "%u byte written at address 0x%8.8" PRIx32 "",
+						  (unsigned int)length,
 						  image.sections[i].base_address + offset);
 		}
 
@@ -2316,8 +2316,8 @@ static int handle_load_image_command(struct command_context_s *cmd_ctx, char *cm
 
 	if (retval == ERROR_OK)
 	{
-		command_print(cmd_ctx, "downloaded %u byte in %s", 
-					  (unsigned int)image_size, 
+		command_print(cmd_ctx, "downloaded %u byte in %s",
+					  (unsigned int)image_size,
 					  duration_text);
 	}
 	free(duration_text);
@@ -2459,8 +2459,8 @@ static int handle_verify_image_command_internal(struct command_context_s *cmd_ct
 		buffer = malloc(image.sections[i].size);
 		if (buffer == NULL)
 		{
-			command_print(cmd_ctx, 
-						  "error allocating buffer for section (%d bytes)", 
+			command_print(cmd_ctx,
+						  "error allocating buffer for section (%d bytes)",
 						  (int)(image.sections[i].size));
 			break;
 		}
@@ -2507,10 +2507,10 @@ static int handle_verify_image_command_internal(struct command_context_s *cmd_ct
 					{
 						if (data[t] != buffer[t])
 						{
-							command_print(cmd_ctx, 
-										  "Verify operation failed address 0x%08x. Was 0x%02x instead of 0x%02x\n", 
-										  (unsigned)(t + image.sections[i].base_address), 
-										  data[t], 
+							command_print(cmd_ctx,
+										  "Verify operation failed address 0x%08x. Was 0x%02x instead of 0x%02x\n",
+										  (unsigned)(t + image.sections[i].base_address),
+										  data[t],
 										  buffer[t]);
 							free(data);
 							free(buffer);
@@ -2528,8 +2528,8 @@ static int handle_verify_image_command_internal(struct command_context_s *cmd_ct
 			}
 		} else
 		{
-			command_print(cmd_ctx, "address 0x%08" PRIx32 " length 0x%08" PRIx32 "", 
-						  image.sections[i].base_address, 
+			command_print(cmd_ctx, "address 0x%08" PRIx32 " length 0x%08" PRIx32 "",
+						  image.sections[i].base_address,
 						  buf_cnt);
 		}
 
@@ -2546,8 +2546,8 @@ done:
 
 	if (retval == ERROR_OK)
 	{
-		command_print(cmd_ctx, "verified %u bytes in %s", 
-					  (unsigned int)image_size, 
+		command_print(cmd_ctx, "verified %u bytes in %s",
+					  (unsigned int)image_size,
 					  duration_text);
 	}
 	free(duration_text);
@@ -2578,7 +2578,7 @@ static int handle_bp_command_list(struct command_context_s *cmd_ctx)
 			char* buf = buf_to_str(breakpoint->orig_instr,
 					breakpoint->length, 16);
 			command_print(cmd_ctx, "0x%8.8" PRIx32 ", 0x%x, %i, 0x%s",
-					breakpoint->address, 
+					breakpoint->address,
 					breakpoint->length,
 					breakpoint->set, buf);
 			free(buf);
@@ -2586,7 +2586,7 @@ static int handle_bp_command_list(struct command_context_s *cmd_ctx)
 		else
 		{
 			command_print(cmd_ctx, "0x%8.8" PRIx32 ", 0x%x, %i",
-						  breakpoint->address, 
+						  breakpoint->address,
 						  breakpoint->length, breakpoint->set);
 		}
 
@@ -2667,9 +2667,9 @@ static int handle_wp_command(struct command_context_s *cmd_ctx, char *cmd, char
 
 		while (watchpoint)
 		{
-			command_print(cmd_ctx, 
-						  "address: 0x%8.8" PRIx32 ", len: 0x%8.8x, r/w/a: %i, value: 0x%8.8" PRIx32 ", mask: 0x%8.8" PRIx32 "", 
-						  watchpoint->address, 
+			command_print(cmd_ctx,
+						  "address: 0x%8.8" PRIx32 ", len: 0x%8.8x, r/w/a: %i, value: 0x%8.8" PRIx32 ", mask: 0x%8.8" PRIx32 "",
+						  watchpoint->address,
 						  watchpoint->length,
 						  (int)(watchpoint->rw),
 						  watchpoint->value,
@@ -3111,8 +3111,8 @@ static int target_mem2array(Jim_Interp *interp, target_t *target, int argc, Jim_
 	} else {
 		char buf[100];
 		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		sprintf(buf, "mem2array address: 0x%08" PRIx32 " is not aligned for %" PRId32 " byte reads", 
-				addr, 
+		sprintf(buf, "mem2array address: 0x%08" PRIx32 " is not aligned for %" PRId32 " byte reads",
+				addr,
 				width);
 		Jim_AppendStrings(interp, Jim_GetResult(interp), buf , NULL);
 		return JIM_ERR;
@@ -3135,9 +3135,9 @@ static int target_mem2array(Jim_Interp *interp, target_t *target, int argc, Jim_
 		retval = target_read_memory(target, addr, width, count, buffer);
 		if (retval != ERROR_OK) {
 			/* BOO !*/
-			LOG_ERROR("mem2array: Read @ 0x%08x, w=%d, cnt=%d, failed", 
-					  (unsigned int)addr, 
-					  (int)width, 
+			LOG_ERROR("mem2array: Read @ 0x%08x, w=%d, cnt=%d, failed",
+					  (unsigned int)addr,
+					  (int)width,
 					  (int)count);
 			Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
 			Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: cannot read memory", NULL);
@@ -3298,8 +3298,8 @@ static int target_array2mem(Jim_Interp *interp, target_t *target, int argc, Jim_
 	} else {
 		char buf[100];
 		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		sprintf(buf, "array2mem address: 0x%08x is not aligned for %d byte reads", 
-				(unsigned int)addr, 
+		sprintf(buf, "array2mem address: 0x%08x is not aligned for %d byte reads",
+				(unsigned int)addr,
 				(int)width);
 		Jim_AppendStrings(interp, Jim_GetResult(interp), buf , NULL);
 		return JIM_ERR;
@@ -3339,9 +3339,9 @@ static int target_array2mem(Jim_Interp *interp, target_t *target, int argc, Jim_
 		retval = target_write_memory(target, addr, width, count, buffer);
 		if (retval != ERROR_OK) {
 			/* BOO !*/
-			LOG_ERROR("array2mem: Write @ 0x%08x, w=%d, cnt=%d, failed", 
-					  (unsigned int)addr, 
-					  (int)width, 
+			LOG_ERROR("array2mem: Write @ 0x%08x, w=%d, cnt=%d, failed",
+					  (unsigned int)addr,
+					  (int)width,
 					  (int)count);
 			Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
 			Jim_AppendStrings(interp, Jim_GetResult(interp), "array2mem: cannot read memory", NULL);
@@ -4443,7 +4443,7 @@ static int handle_fast_load_image_command(struct command_context_s *cmd_ctx, cha
 		buffer = malloc(image.sections[i].size);
 		if (buffer == NULL)
 		{
-			command_print(cmd_ctx, "error allocating buffer for section (%d bytes)", 
+			command_print(cmd_ctx, "error allocating buffer for section (%d bytes)",
 						  (int)(image.sections[i].size));
 			break;
 		}
@@ -4486,8 +4486,8 @@ static int handle_fast_load_image_command(struct command_context_s *cmd_ctx, cha
 			fastload[i].length = length;
 
 			image_size += length;
-			command_print(cmd_ctx, "%u byte written at address 0x%8.8x", 
-						  (unsigned int)length, 
+			command_print(cmd_ctx, "%u byte written at address 0x%8.8x",
+						  (unsigned int)length,
 						  ((unsigned int)(image.sections[i].base_address + offset)));
 		}
 
@@ -4528,8 +4528,8 @@ static int handle_fast_load_command(struct command_context_s *cmd_ctx, char *cmd
 	for (i = 0; i < fastload_num;i++)
 	{
 		target_t *target = get_current_target(cmd_ctx);
-		command_print(cmd_ctx, "Write to 0x%08x, length 0x%08x", 
-					  (unsigned int)(fastload[i].address), 
+		command_print(cmd_ctx, "Write to 0x%08x, length 0x%08x",
+					  (unsigned int)(fastload[i].address),
 					  (unsigned int)(fastload[i].length));
 		if (retval == ERROR_OK)
 		{
@@ -4544,7 +4544,7 @@ static int handle_fast_load_command(struct command_context_s *cmd_ctx, char *cmd
 
 
 /*
- * Local Variables: 
+ * Local Variables:
  * c-basic-offset: 4
  * tab-width: 4
  * End:
diff --git a/src/target/trace.c b/src/target/trace.c
index 7d137d6c..9387f830 100644
--- a/src/target/trace.c
+++ b/src/target/trace.c
@@ -30,7 +30,7 @@ int trace_point(target_t *target, uint32_t number)
 	trace_t *trace = target->trace_info;
 
 	LOG_DEBUG("tracepoint: %i", (int)number);
-	
+
 	if (number < trace->num_trace_points)
 		trace->trace_points[number].hit_counter++;
 
@@ -43,7 +43,7 @@ int trace_point(target_t *target, uint32_t number)
 			trace->trace_history_overflowed = 1;
 		}
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -51,11 +51,11 @@ static int handle_trace_point_command(struct command_context_s *cmd_ctx, char *c
 {
 	target_t *target = get_current_target(cmd_ctx);
 	trace_t *trace = target->trace_info;
-	
+
 	if (argc == 0)
 	{
 		uint32_t i;
-		
+
 		for (i = 0; i < trace->num_trace_points; i++)
 		{
 			command_print(cmd_ctx, "trace point 0x%8.8" PRIx32 " (%lld times hit)",
@@ -65,7 +65,7 @@ static int handle_trace_point_command(struct command_context_s *cmd_ctx, char *c
 
 		return ERROR_OK;
 	}
-	
+
 	if (!strcmp(args[0], "clear"))
 	{
 		if (trace->trace_points)
@@ -75,21 +75,21 @@ static int handle_trace_point_command(struct command_context_s *cmd_ctx, char *c
 		}
 		trace->num_trace_points = 0;
 		trace->trace_points_size = 0;
-		
+
 		return ERROR_OK;
 	}
-	
+
 	/* resize array if necessary */
 	if (!trace->trace_points || (trace->trace_points_size == trace->num_trace_points))
 	{
 		trace->trace_points = realloc(trace->trace_points, sizeof(trace_point_t) * (trace->trace_points_size + 32));
 		trace->trace_points_size += 32;
 	}
-	
+
 	trace->trace_points[trace->num_trace_points].address = strtoul(args[0], NULL, 0);
 	trace->trace_points[trace->num_trace_points].hit_counter = 0;
 	trace->num_trace_points++;
-	
+
 	return ERROR_OK;
 }
 
@@ -97,7 +97,7 @@ static int handle_trace_history_command(struct command_context_s *cmd_ctx, char
 {
 	target_t *target = get_current_target(cmd_ctx);
 	trace_t *trace = target->trace_info;
-	
+
 	if (argc > 0)
 	{
 		trace->trace_history_pos = 0;
@@ -108,13 +108,13 @@ static int handle_trace_history_command(struct command_context_s *cmd_ctx, char
 			/* clearing is implicit, we've just reset position anyway */
 			return ERROR_OK;
 		}
-		
+
 		if (trace->trace_history)
 			free(trace->trace_history);
-		
+
 		trace->trace_history_size = strtoul(args[0], NULL, 0);
 		trace->trace_history = malloc(sizeof(uint32_t) * trace->trace_history_size);
-		
+
 		command_print(cmd_ctx, "new trace history size: %i", (int)(trace->trace_history_size));
 	}
 	else
@@ -132,7 +132,7 @@ static int handle_trace_history_command(struct command_context_s *cmd_ctx, char
 			first = trace->trace_history_pos;
 			last = trace->trace_history_pos - 1;
 		}
-		
+
 		for (i = first; (i % trace->trace_history_size) != last; i++)
 		{
 			if (trace->trace_history[i % trace->trace_history_size] < trace->num_trace_points)
@@ -158,7 +158,7 @@ int trace_register_commands(struct command_context_s *cmd_ctx)
 {
 	command_t *trace_cmd =
 		register_command(cmd_ctx, NULL, "trace", NULL, COMMAND_ANY, "trace commands");
-	
+
 	register_command(cmd_ctx, trace_cmd, "history", handle_trace_history_command,
 		COMMAND_EXEC, "display trace history, ['clear'] history or set [size]");
 
diff --git a/src/target/xscale.h b/src/target/xscale.h
index 8015c2bb..b993f4c9 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -34,7 +34,7 @@ typedef struct xscale_jtag_s
 	/* position in JTAG scan chain */
 	jtag_tap_t *tap;
 
-	/* IR length and instructions */	
+	/* IR length and instructions */
 	int ir_length;
 	uint32_t dbgrx;
 	uint32_t dbgtx;
@@ -86,7 +86,7 @@ typedef struct xscale_trace_s
 typedef struct xscale_common_s
 {
 	int common_magic;
-	
+
 	/* XScale registers (CP15, DBG) */
 	reg_cache_t *reg_cache;
 
@@ -94,29 +94,29 @@ typedef struct xscale_common_s
 	char *variant;
 
 	xscale_jtag_t jtag_info;
-	
+
 	/* current state of the debug handler */
 	int handler_installed;
 	int handler_running;
 	uint32_t handler_address;
-	
+
 	/* target-endian buffers with exception vectors */
 	uint32_t low_vectors[8];
 	uint32_t high_vectors[8];
-	
+
 	/* static low vectors */
 	uint8_t static_low_vectors_set;	/* bit field with static vectors set by the user */
 	uint8_t static_high_vectors_set; /* bit field with static vectors set by the user */
 	uint32_t static_low_vectors[8];
 	uint32_t static_high_vectors[8];
 
-	/* DCache cleaning */	
+	/* DCache cleaning */
 	uint32_t cache_clean_address;
-	
+
 	/* whether hold_rst and ext_dbg_break should be set */
 	int hold_rst;
 	int external_debug_break;
-	
+
 	/* breakpoint / watchpoint handling */
 	int dbr_available;
 	int dbr0_used;
@@ -126,23 +126,23 @@ typedef struct xscale_common_s
 	int	ibcr1_used;
 	uint32_t arm_bkpt;
 	uint16_t thumb_bkpt;
-	
+
 	uint8_t vector_catch;
 
 	xscale_trace_t trace;
-	
+
 	int arch_debug_reason;
-	
+
 	/* armv4/5 common stuff */
 	armv4_5_common_t armv4_5_common;
-	
+
 	/* MMU/Caches */
 	armv4_5_mmu_common_t armv4_5_mmu;
 	uint32_t cp15_control_reg;
-	
+
 	/* possible future enhancements that go beyond XScale common stuff */
 	void *arch_info;
-	
+
 	int fast_memory_access;
 } xscale_common_t;
 
diff --git a/src/target/xscale/protocol.h b/src/target/xscale/protocol.h
index 525db31d..aabbc2dc 100644
--- a/src/target/xscale/protocol.h
+++ b/src/target/xscale/protocol.h
@@ -37,10 +37,10 @@
 #define REG_CPSR 16
 #define REG_SPSR 17
 
-#define MODE_USR 0x10 
+#define MODE_USR 0x10
 #define MODE_FIQ 0x11
-#define MODE_IRQ 0x12 
-#define MODE_SVC 0x13 
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
 #define MODE_ABT 0x17
 #define MODE_UND 0x1b
 #define MODE_SYS 0x1f