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authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-11-05 09:06:34 +0000
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-11-05 09:06:34 +0000
commit3dd0884989fd36d13cd1907c3ca8ccd38eed763f (patch)
treee7cb1b05df9f2131ad70fd2beb59fc6c8bd731fb /src/target
parent71c73068858ad80020c7956a215a5ec590704ddb (diff)
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git-svn-id: svn://svn.berlios.de/openocd/trunk@1136 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target')
-rw-r--r--src/target/target/imote2.cfg24
-rw-r--r--src/target/target/is5114.cfg20
-rw-r--r--src/target/target/str910-eval.cfg19
3 files changed, 63 insertions, 0 deletions
diff --git a/src/target/target/imote2.cfg b/src/target/target/imote2.cfg
new file mode 100644
index 00000000..a02a8d3c
--- /dev/null
+++ b/src/target/target/imote2.cfg
@@ -0,0 +1,24 @@
+# iMote2
+#
+# PXA271 and an Intel Strataflash of 32 Megabytes (p30)
+#
+# Marvell/Intel PXA270 Script
+# set jtag_nsrst_delay to the delay introduced by your reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_nsrst_delay 800
+# set the jtag_ntrst_delay to the delay introduced by a reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_ntrst_delay 0
+#use combined on interfaces or targets that can’t set TRST/SRST separately
+reset_config trst_and_srst separate
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 7 0x1 0x7f 0x7e
+target xscale little 0 pxa27x
+# maps to PXA internal RAM. If you are using a PXA255
+# you must initialize SDRAM or leave this option off
+working_area 0 0x5c000000 0x10000 nobackup
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+# works for P30 flash
+flash bank cfi 0x00000000 0x2000000 2 2 0
diff --git a/src/target/target/is5114.cfg b/src/target/target/is5114.cfg
new file mode 100644
index 00000000..a370ff3d
--- /dev/null
+++ b/src/target/target/is5114.cfg
@@ -0,0 +1,20 @@
+# script for Insilica IS-5114
+
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+jtag_rclk 16
+
+reset_config trst_and_srst
+
+jtag_device 8 0x1 0x1 0xfe
+jtag_device 4 0x1 0xf 0xe
+jtag_device 5 0x1 0x1 0x1e
+
+#arm946e-s and
+target arm966e little 1 arm966e
+
+[new_target_name] configure -event reset-start { jtag_rclk 16 }
+[new_target_name] configure -event reset-init {
+ # We can increase speed now that we know the target is halted.
+ jtag_rclk 3000
+}
+working_area 0 0x50000000 16384 nobackup
diff --git a/src/target/target/str910-eval.cfg b/src/target/target/str910-eval.cfg
new file mode 100644
index 00000000..b77e0eaa
--- /dev/null
+++ b/src/target/target/str910-eval.cfg
@@ -0,0 +1,19 @@
+# str910-eval eval board
+#
+# Need reset scripts
+reset_config trst_and_srst
+
+jtag_device 8 0x1 0x1 0xfe
+jtag_device 4 0x1 0xf 0xe
+jtag_device 5 0x1 0x1 0x1e
+
+target arm966e little reset_halt 1 arm966e
+
+working_area 0 0x50000000 16384 nobackup
+
+flash bank str9xpec 0x00000000 0x00080000 0 0 0
+
+str9xpec enable_turbo 0
+str9xpec options_read 0
+str9xpec options_cmap 0 bank 1
+str9xpec options_write 0