summaryrefslogtreecommitdiff
path: root/src/target
diff options
context:
space:
mode:
authorMike Dunn <mikedunn@newsguy.com>2010-03-18 21:34:13 -0700
committerDavid Brownell <dbrownell@users.sourceforge.net>2010-03-18 21:34:13 -0700
commit8d411d0d249dda7ceb951c4f8c8a509f4fd1dfb0 (patch)
tree324c00806bb00979d92340a6afd3217582e080f0 /src/target
parentfc9de56a251a7cfc2610cc1904a69fc7b9fd3011 (diff)
downloadopenocd+libswd-8d411d0d249dda7ceb951c4f8c8a509f4fd1dfb0.tar.gz
openocd+libswd-8d411d0d249dda7ceb951c4f8c8a509f4fd1dfb0.tar.bz2
openocd+libswd-8d411d0d249dda7ceb951c4f8c8a509f4fd1dfb0.tar.xz
openocd+libswd-8d411d0d249dda7ceb951c4f8c8a509f4fd1dfb0.zip
Fix underlying problem with xscale icache and dcache commands
Fix problem with the xscale icache and dcache commands. Both commands were enabling or disabling the mmu, not the caches I didn't look any further after my earlier patch fixed the trivial problem with command argument parsing. Turns out the underlying code was broken. The resolution is straightforward when you look at the arguments to xscale_enable_mmu_caches() and xscale_disable_mmu_caches(). I finally took a deeper look after dumping the cp15 control register (XSCALE_CTRL) and seeing that the cache bits weren't changing, but the mmu bit was (which caused all manner of grief, as you can imagine). This has been tested and works OK now. src/target/xscale.c | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target')
-rw-r--r--src/target/xscale.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/src/target/xscale.c b/src/target/xscale.c
index f5aada50..55323ae3 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3204,14 +3204,19 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
{
bool enable;
COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
- if (enable)
- xscale_enable_mmu_caches(target, 1, 0, 0);
- else
- xscale_disable_mmu_caches(target, 1, 0, 0);
- if (icache)
+ if (icache) {
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
- else
+ if (enable)
+ xscale_enable_mmu_caches(target, 0, 0, 1);
+ else
+ xscale_disable_mmu_caches(target, 0, 0, 1);
+ } else {
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
+ if (enable)
+ xscale_enable_mmu_caches(target, 0, 1, 0);
+ else
+ xscale_disable_mmu_caches(target, 0, 1, 0);
+ }
}
bool enabled = icache ?