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author | Michel JAOUEN <michel.jaouen@stericsson.com> | 2011-04-12 18:09:18 +0200 |
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committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-04-13 10:56:42 +0200 |
commit | a7844aa4e83481a66fd5df8f33956da586d2f880 (patch) | |
tree | 3980c933e6f40a3eb9627624b536141e5032f8d5 /src/target | |
parent | d6027ca6a81dfde3c2ce09712ca256b00c8047a1 (diff) | |
download | openocd+libswd-a7844aa4e83481a66fd5df8f33956da586d2f880.tar.gz openocd+libswd-a7844aa4e83481a66fd5df8f33956da586d2f880.tar.bz2 openocd+libswd-a7844aa4e83481a66fd5df8f33956da586d2f880.tar.xz openocd+libswd-a7844aa4e83481a66fd5df8f33956da586d2f880.zip |
cortex_a : use dap ref from armv4_5common
Diffstat (limited to 'src/target')
-rw-r--r-- | src/target/cortex_a.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 5fad309a..f81f0693 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -81,7 +81,7 @@ static int cortex_a8_get_ttb(struct target *target, uint32_t *result); static int cortex_a8_init_debug_access(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; int retval; uint32_t dummy; @@ -129,7 +129,7 @@ static int cortex_a8_exec_opcode(struct target *target, uint32_t dscr; int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; dscr = dscr_p ? *dscr_p : 0; @@ -191,7 +191,7 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre { int retval = ERROR_OK; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0); if (retval != ERROR_OK) @@ -216,7 +216,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, uint8_t reg = regnum&0xFF; uint32_t dscr = 0; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; if (reg > 17) return retval; @@ -286,7 +286,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint8_t Rd = regnum&0xFF; uint32_t dscr; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); @@ -369,7 +369,7 @@ static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_ { int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, address, value); @@ -395,14 +395,14 @@ static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm) static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data) { LOG_DEBUG("write DCC 0x%08" PRIx32, data); - return mem_ap_sel_write_u32(&a8->armv7a_common.dap, swjdp_debugap, - a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); + return mem_ap_sel_write_u32(a8->armv7a_common.armv4_5_common.dap, + swjdp_debugap,a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); } static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, uint32_t *dscr_p) { - struct adiv5_dap *swjdp = &a8->armv7a_common.dap; + struct adiv5_dap *swjdp = a8->armv7a_common.armv4_5_common.dap; uint32_t dscr = DSCR_INSTR_COMP; int retval; @@ -439,7 +439,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); - struct adiv5_dap *swjdp = &a8->armv7a_common.dap; + struct adiv5_dap *swjdp = a8->armv7a_common.armv4_5_common.dap; uint32_t dscr; int retval; @@ -682,7 +682,7 @@ static int cortex_a8_poll(struct target *target) uint32_t dscr; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; enum target_state prev_target_state = target->state; retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, @@ -741,7 +741,7 @@ static int cortex_a8_halt(struct target *target) int retval = ERROR_OK; uint32_t dscr; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; /* * Tell the core to be halted by writing DRCR with 0x1 @@ -793,7 +793,7 @@ static int cortex_a8_resume(struct target *target, int current, { struct armv7a_common *armv7a = target_to_armv7a(target); struct arm *armv4_5 = &armv7a->armv4_5_common; - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; int retval; // struct breakpoint *breakpoint = NULL; @@ -945,7 +945,7 @@ static int cortex_a8_debug_entry(struct target *target) struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = target_to_armv7a(target); struct arm *armv4_5 = &armv7a->armv4_5_common; - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; struct reg *reg; LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); @@ -1461,7 +1461,7 @@ static int cortex_a8_read_phys_memory(struct target *target, uint32_t count, uint8_t *buffer) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; int retval = ERROR_INVALID_ARGUMENTS; uint8_t apsel = swjdp->apsel; @@ -1590,7 +1590,7 @@ static int cortex_a8_write_phys_memory(struct target *target, uint32_t count, const uint8_t *buffer) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; int retval = ERROR_INVALID_ARGUMENTS; uint8_t apsel = swjdp->apsel; @@ -1784,7 +1784,7 @@ static int cortex_a8_handle_target_request(void *priv) { struct target *target = priv; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; int retval; if (!target_was_examined(target)) @@ -1824,7 +1824,7 @@ static int cortex_a8_examine_first(struct target *target) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; int i; int retval = ERROR_OK; uint32_t didr, ctypr, ttypr, cpuid; |