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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-01-14 15:25:45 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-01-14 15:25:45 +0000 |
| commit | c01e095d030d4e7a7e6917b7cfbab2e77463f958 (patch) | |
| tree | 1cf8629d91f6732b1fb6e8f6c4ab8a397e9c69d3 /src/target | |
| parent | 882a2712052d25fc15535e6199b4c663a5280c20 (diff) | |
| download | openocd+libswd-c01e095d030d4e7a7e6917b7cfbab2e77463f958.tar.gz openocd+libswd-c01e095d030d4e7a7e6917b7cfbab2e77463f958.tar.bz2 openocd+libswd-c01e095d030d4e7a7e6917b7cfbab2e77463f958.tar.xz openocd+libswd-c01e095d030d4e7a7e6917b7cfbab2e77463f958.zip | |
arm11 wip
git-svn-id: svn://svn.berlios.de/openocd/trunk@1317 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/target/imx31.cfg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/target/imx31.cfg b/src/target/target/imx31.cfg index 3d4883b7..3fed2f82 100644 --- a/src/target/target/imx31.cfg +++ b/src/target/target/imx31.cfg @@ -45,14 +45,14 @@ jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJ # SDMA_BYPASS - disables SDMA - # # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID # No IDCODE for this TAP jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0 # Per section 40.17.1, table 40-85 the IR register is 4 bits # But this conflicts with Diagram 6-13, "3bits ir and drs" -jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_SDMATAPID +jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID set _TARGETNAME [format "%s.cpu" $_CHIPNAME] target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME |