swjdp_common_t -> struct swjdp_common

Remove misleading typedef and redundant suffix from struct swjdp_common.

8 files changed, 113 insertions, 113 deletions

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 7fc22d0e..3323485e 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -71,7 +71,7 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address
 ***************************************************************************/
 
 /* Scan out and in from target ordered uint8_t buffers */
-int adi_jtag_dp_scan(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
+int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 {
 	arm_jtag_t *jtag_info = swjdp->jtag_info;
 	struct scan_field fields[2];
@@ -101,7 +101,7 @@ int adi_jtag_dp_scan(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uin
 }
 
 /* Scan out and in from host ordered uint32_t variables */
-int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
+int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 {
 	arm_jtag_t *jtag_info = swjdp->jtag_info;
 	struct scan_field fields[2];
@@ -143,7 +143,7 @@ int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr,
 }
 
 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
-int scan_inout_check(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue)
+int scan_inout_check(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue)
 {
 	adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 
@@ -161,7 +161,7 @@ int scan_inout_check(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uin
 	return ERROR_OK;
 }
 
-int scan_inout_check_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue)
+int scan_inout_check_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue)
 {
 	adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 
@@ -179,7 +179,7 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr,
 	return ERROR_OK;
 }
 
-int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
+int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
 {
 	int retval;
 	uint32_t ctrlstat;
@@ -287,17 +287,17 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
  *                                                                         *
 ***************************************************************************/
 
-int dap_dp_write_reg(swjdp_common_t *swjdp, uint32_t value, uint8_t reg_addr)
+int dap_dp_write_reg(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr)
 {
 	return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
 }
 
-int dap_dp_read_reg(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr)
+int dap_dp_read_reg(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr)
 {
 	return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
 }
 
-int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel)
+int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 {
 	uint32_t select;
 	select = (apsel << 24) & 0xFF000000;
@@ -314,7 +314,7 @@ int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel)
 	return ERROR_OK;
 }
 
-int dap_dp_bankselect(swjdp_common_t *swjdp,uint32_t ap_reg)
+int dap_dp_bankselect(struct swjdp_common *swjdp,uint32_t ap_reg)
 {
 	uint32_t select;
 	select = (ap_reg & 0x000000F0);
@@ -328,7 +328,7 @@ int dap_dp_bankselect(swjdp_common_t *swjdp,uint32_t ap_reg)
 	return ERROR_OK;
 }
 
-int dap_ap_write_reg(swjdp_common_t *swjdp, uint32_t reg_addr, uint8_t* out_value_buf)
+int dap_ap_write_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t* out_value_buf)
 {
 	dap_dp_bankselect(swjdp, reg_addr);
 	scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
@@ -336,14 +336,14 @@ int dap_ap_write_reg(swjdp_common_t *swjdp, uint32_t reg_addr, uint8_t* out_valu
 	return ERROR_OK;
 }
 
-int dap_ap_read_reg(swjdp_common_t *swjdp, uint32_t reg_addr, uint8_t *in_value_buf)
+int dap_ap_read_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t *in_value_buf)
 {
 	dap_dp_bankselect(swjdp, reg_addr);
 	scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
 
 	return ERROR_OK;
 }
-int dap_ap_write_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t value)
+int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
 {
 	uint8_t out_value_buf[4];
 
@@ -354,7 +354,7 @@ int dap_ap_write_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t valu
 	return ERROR_OK;
 }
 
-int dap_ap_read_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t *value)
+int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
 {
 	dap_dp_bankselect(swjdp, reg_addr);
 	scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value);
@@ -368,7 +368,7 @@ int dap_ap_read_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t *valu
  *                                                                         *
 ***************************************************************************/
 
-int dap_setup_accessport(swjdp_common_t *swjdp, uint32_t csw, uint32_t tar)
+int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 {
 	csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 	if (csw != swjdp->ap_csw_value)
@@ -393,13 +393,13 @@ int dap_setup_accessport(swjdp_common_t *swjdp, uint32_t csw, uint32_t tar)
 
 /*****************************************************************************
 *                                                                            *
-* mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value)      *
+* mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)      *
 *                                                                            *
 * Read a uint32_t value from memory or system register                            *
 * Functionally equivalent to target_read_u32(target, address, uint32_t *value),   *
 * but with less overhead                                                     *
 *****************************************************************************/
-int mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value)
+int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 {
 	swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 
@@ -409,7 +409,7 @@ int mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value)
 	return ERROR_OK;
 }
 
-int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value)
+int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 {
 	mem_ap_read_u32(swjdp, address, value);
 
@@ -418,12 +418,12 @@ int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *va
 
 /*****************************************************************************
 *                                                                            *
-* mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value)      *
+* mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)      *
 *                                                                            *
 * Write a uint32_t value to memory or memory mapped register                              *
 *                                                                            *
 *****************************************************************************/
-int mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value)
+int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 {
 	swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 
@@ -433,7 +433,7 @@ int mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value)
 	return ERROR_OK;
 }
 
-int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value)
+int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 {
 	mem_ap_write_u32(swjdp, address, value);
 
@@ -442,12 +442,12 @@ int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t va
 
 /*****************************************************************************
 *                                                                            *
-* mem_ap_write_buf(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) *
+* mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 *                                                                            *
 * Write a buffer in target order (little endian)                             *
 *                                                                            *
 *****************************************************************************/
-int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 {
 	int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 	uint32_t adr = address;
@@ -516,7 +516,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint
 	return retval;
 }
 
-int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 {
 	int retval = ERROR_OK;
 	int wcount, blocksize, writecount, i;
@@ -587,7 +587,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int coun
 	return retval;
 }
 
-int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 {
 	int retval = ERROR_OK;
 
@@ -612,7 +612,7 @@ int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint
 	return retval;
 }
 
-int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 {
 	int retval = ERROR_OK;
 	int wcount, blocksize, writecount, i;
@@ -679,7 +679,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count
 	return retval;
 }
 
-int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 {
 	int retval = ERROR_OK;
 
@@ -704,12 +704,12 @@ int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3
 
 /*********************************************************************************
 *                                                                                *
-* mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)  *
+* mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)  *
 *                                                                                *
 * Read block fast in target order (little endian) into a buffer                  *
 *                                                                                *
 **********************************************************************************/
-int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 {
 	int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 	uint32_t adr = address;
@@ -782,7 +782,7 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3
 	return retval;
 }
 
-int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 {
 	uint32_t invalue;
 	int retval = ERROR_OK;
@@ -834,7 +834,7 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count
 	return retval;
 }
 
-int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 {
 	uint32_t invalue, i;
 	int retval = ERROR_OK;
@@ -877,7 +877,7 @@ int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3
  * The solution is to arrange for a large out/in scan in this loop and
  * and convert data afterwards.
  */
-int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 {
 	uint32_t invalue;
 	int retval = ERROR_OK;
@@ -926,7 +926,7 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count,
 	return retval;
 }
 
-int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 {
 	uint32_t invalue;
 	int retval = ERROR_OK;
@@ -950,7 +950,7 @@ int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32
 	return retval;
 }
 
-int ahbap_debugport_init(swjdp_common_t *swjdp)
+int ahbap_debugport_init(struct swjdp_common *swjdp)
 {
 	uint32_t idreg, romaddr, dummy;
 	uint32_t ctrlstat;
@@ -1022,7 +1022,7 @@ is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 			&& ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 }
 
-int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel)
+int dap_info_command(struct command_context_s *cmd_ctx, struct swjdp_common *swjdp, int apsel)
 {
 
 	uint32_t dbgbase,apid;
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index a52a0964..5f2c9697 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -82,7 +82,7 @@ struct swjdp_reg
 	arm_jtag_t *jtag_info;
 };
 
-typedef struct swjdp_common_s
+struct swjdp_common
 {
 	arm_jtag_t *jtag_info;
 	/* Control config */
@@ -102,65 +102,65 @@ typedef struct swjdp_common_s
 	/* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
 	uint32_t tar_autoincr_block;
 
-} swjdp_common_t;
+};
 
 /* Accessor function for currently selected DAP-AP number */
-static inline uint8_t dap_ap_get_select(swjdp_common_t *swjdp)
+static inline uint8_t dap_ap_get_select(struct swjdp_common *swjdp)
 {
 	return (uint8_t)(swjdp ->apsel >> 24);
 }
 
 /* Internal functions used in the module, partial transactions, use with caution */
-int dap_dp_write_reg(swjdp_common_t *swjdp, uint32_t value, uint8_t reg_addr);
-/* int swjdp_write_apacc(swjdp_common_t *swjdp, uint32_t value, uint8_t reg_addr); */
-int dap_dp_read_reg(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr);
-/* int swjdp_read_apacc(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr); */
-int dap_setup_accessport(swjdp_common_t *swjdp, uint32_t csw, uint32_t tar);
-int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel);
-
-int dap_ap_write_reg(swjdp_common_t *swjdp, uint32_t addr, uint8_t* out_buf);
-int dap_ap_write_reg_u32(swjdp_common_t *swjdp, uint32_t addr, uint32_t value);
-int dap_ap_read_reg(swjdp_common_t *swjdp, uint32_t addr, uint8_t *in_buf);
-int dap_ap_read_reg_u32(swjdp_common_t *swjdp, uint32_t addr, uint32_t *value);
+int dap_dp_write_reg(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr);
+/* int swjdp_write_apacc(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr); */
+int dap_dp_read_reg(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr);
+/* int swjdp_read_apacc(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr); */
+int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar);
+int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel);
+
+int dap_ap_write_reg(struct swjdp_common *swjdp, uint32_t addr, uint8_t* out_buf);
+int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t addr, uint32_t value);
+int dap_ap_read_reg(struct swjdp_common *swjdp, uint32_t addr, uint8_t *in_buf);
+int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t addr, uint32_t *value);
 
 /* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
-int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
+int swjdp_transaction_endcheck(struct swjdp_common *swjdp);
 
 /* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */
-int mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value);
-int mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value);
+int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
+int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value);
 
 /* MEM-AP memory mapped bus transfers, single registers, complete transactions */
-int mem_ap_read_atomic_u32(swjdp_common_t *swjdp,
+int mem_ap_read_atomic_u32(struct swjdp_common *swjdp,
 		uint32_t address, uint32_t *value);
-int mem_ap_write_atomic_u32(swjdp_common_t *swjdp,
+int mem_ap_write_atomic_u32(struct swjdp_common *swjdp,
 		uint32_t address, uint32_t value);
 
 /* MEM-AP memory mapped bus block transfers */
-int mem_ap_read_buf_u8(swjdp_common_t *swjdp,
+int mem_ap_read_buf_u8(struct swjdp_common *swjdp,
 		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u16(swjdp_common_t *swjdp,
+int mem_ap_read_buf_u16(struct swjdp_common *swjdp,
 		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u32(swjdp_common_t *swjdp,
+int mem_ap_read_buf_u32(struct swjdp_common *swjdp,
 		uint8_t *buffer, int count, uint32_t address);
 
-int mem_ap_write_buf_u8(swjdp_common_t *swjdp,
+int mem_ap_write_buf_u8(struct swjdp_common *swjdp,
 		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u16(swjdp_common_t *swjdp,
+int mem_ap_write_buf_u16(struct swjdp_common *swjdp,
 		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u32(swjdp_common_t *swjdp,
+int mem_ap_write_buf_u32(struct swjdp_common *swjdp,
 		uint8_t *buffer, int count, uint32_t address);
 
 /* Initialisation of the debug system, power domains and registers */
-int ahbap_debugport_init(swjdp_common_t *swjdp);
+int ahbap_debugport_init(struct swjdp_common *swjdp);
 
 
 /* Commands for user dap access */
 int dap_info_command(struct command_context_s *cmd_ctx,
-		swjdp_common_t *swjdp, int apsel);
+		struct swjdp_common *swjdp, int apsel);
 
 #define DAP_COMMAND_HANDLER(name) \
-		COMMAND_HELPER(name, swjdp_common_t *swjdp)
+		COMMAND_HELPER(name, struct swjdp_common *swjdp)
 DAP_COMMAND_HANDLER(dap_baseaddr_command);
 DAP_COMMAND_HANDLER(dap_memaccess_command);
 DAP_COMMAND_HANDLER(dap_apsel_command);
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index eb5bfa9e..0bba549f 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -234,7 +234,7 @@ COMMAND_HANDLER(handle_dap_baseaddr_command)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	return CALL_COMMAND_HANDLER(dap_baseaddr_command, swjdp);
 }
@@ -243,7 +243,7 @@ COMMAND_HANDLER(handle_dap_memaccess_command)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp);
 }
@@ -252,7 +252,7 @@ COMMAND_HANDLER(handle_dap_apsel_command)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp);
 }
@@ -261,7 +261,7 @@ COMMAND_HANDLER(handle_dap_apid_command)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	return CALL_COMMAND_HANDLER(dap_apid_command, swjdp);
 }
@@ -270,7 +270,7 @@ COMMAND_HANDLER(handle_dap_info_command)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 	uint32_t apsel;
 
 	switch (argc) {
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 2ad0321f..e7a7fc25 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -97,7 +97,7 @@ typedef struct armv7a_common_s
 	enum armv7a_state core_state;
 
 	/* arm adp debug port */
-	swjdp_common_t swjdp_info;
+	struct swjdp_common swjdp_info;
 
 	/* Core Debug Unit */
 	uint32_t debug_base;
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 0e3c8a9c..62be15e6 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -749,7 +749,7 @@ COMMAND_HANDLER(handle_dap_baseaddr_command)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 	uint32_t apsel, apselsave, baseaddr;
 	int retval;
 
@@ -786,7 +786,7 @@ COMMAND_HANDLER(handle_dap_apid_command)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
 	return CALL_COMMAND_HANDLER(dap_apid_command, swjdp);
 }
@@ -795,7 +795,7 @@ COMMAND_HANDLER(handle_dap_apsel_command)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
 	return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp);
 }
@@ -804,7 +804,7 @@ COMMAND_HANDLER(handle_dap_memaccess_command)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
 	return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp);
 }
@@ -814,7 +814,7 @@ COMMAND_HANDLER(handle_dap_info_command)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 	uint32_t apsel;
 
 	switch (argc) {
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 75ba3d94..8e87c779 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -97,7 +97,7 @@ typedef struct armv7m_common_s
 	reg_cache_t *core_cache;
 	enum armv7m_mode core_mode;
 	int exception_number;
-	swjdp_common_t swjdp_info;
+	struct swjdp_common swjdp_info;
 
 	/* Direct processor core register read and writes */
 	int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 2a3cbadd..7f0189b2 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -65,7 +65,7 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target,
 static int cortex_a8_init_debug_access(target_t *target)
 {
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	int retval;
 	uint32_t dummy;
@@ -95,7 +95,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
 	uint32_t dscr;
 	int retval;
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
 	do
@@ -136,7 +136,7 @@ static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
 {
 	int retval = ERROR_OK;
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
 	cortex_a8_dap_write_coreregister_u32(target, address, 0);
@@ -153,7 +153,7 @@ static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
 {
 	int retval;
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2));
 	/* Move R0 to DTRTX */
@@ -172,7 +172,7 @@ static int cortex_a8_write_cp(target_t *target, uint32_t value,
 	int retval;
 	uint32_t dscr;
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value);
 
@@ -236,7 +236,7 @@ static int cortex_a8_dap_read_coreregister_u32(target_t *target,
 	uint8_t reg = regnum&0xFF;
 	uint32_t dscr;
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	if (reg > 16)
 		return retval;
@@ -277,7 +277,7 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value
 	uint8_t Rd = regnum&0xFF;
 	uint32_t dscr;
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
 
@@ -324,7 +324,7 @@ static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t add
 {
 	int retval;
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	retval = mem_ap_write_atomic_u32(swjdp, address, value);
 
@@ -341,7 +341,7 @@ static int cortex_a8_poll(target_t *target)
 	uint32_t dscr;
 	struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 	enum target_state prev_target_state = target->state;
 	uint8_t saved_apsel = dap_ap_get_select(swjdp);
 
@@ -405,7 +405,7 @@ static int cortex_a8_halt(target_t *target)
 	int retval = ERROR_OK;
 	uint32_t dscr;
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 	uint8_t saved_apsel = dap_ap_get_select(swjdp);
 	dap_ap_select(swjdp, swjdp_debugap);
 
@@ -443,7 +443,7 @@ static int cortex_a8_resume(struct target_s *target, int current,
 {
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
 	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 //	breakpoint_t *breakpoint = NULL;
 	uint32_t resume_pc, dscr;
@@ -568,7 +568,7 @@ static int cortex_a8_debug_entry(target_t *target)
 	struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
 	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
@@ -1179,7 +1179,7 @@ static int cortex_a8_read_memory(struct target_s *target, uint32_t address,
 		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	int retval = ERROR_OK;
 
@@ -1214,7 +1214,7 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
 		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	int retval;
 
@@ -1271,7 +1271,7 @@ static int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
 }
 
 
-static int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
 {
 #if 0
 	u16 dcrdr;
@@ -1300,7 +1300,7 @@ static int cortex_a8_handle_target_request(void *priv)
 	if (!target->type->examined)
 		return ERROR_OK;
 	struct armv7a_common_s *armv7a = target_to_armv7a(target);
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	if (!target->dbg_msg_enabled)
 		return ERROR_OK;
@@ -1340,7 +1340,7 @@ static int cortex_a8_examine(struct target_s *target)
 {
 	struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 	int i;
 	int retval = ERROR_OK;
 	uint32_t didr, ctypr, ttypr, cpuid;
@@ -1458,7 +1458,7 @@ int cortex_a8_init_arch_info(target_t *target,
 
 	armv7a = &cortex_a8->armv7a_common;
 	armv4_5 = &armv7a->armv4_5_common;
-	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	/* Setup cortex_a8_common_t */
 	cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index d617817d..ae714462 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -56,7 +56,7 @@ extern uint8_t armv7m_gdb_dummy_cpsr_value[];
 extern reg_t armv7m_gdb_dummy_cpsr_reg;
 #endif
 
-static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp,
+static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
 		uint32_t *value, int regnum)
 {
 	int retval;
@@ -87,7 +87,7 @@ static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp,
 	return retval;
 }
 
-static int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp,
+static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
 		uint32_t value, int regnum)
 {
 	int retval;
@@ -122,7 +122,7 @@ static int cortex_m3_write_debug_halt_mask(target_t *target,
 		uint32_t mask_on, uint32_t mask_off)
 {
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-	struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+	struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 
 	/* mask off status bits */
 	cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
@@ -135,7 +135,7 @@ static int cortex_m3_write_debug_halt_mask(target_t *target,
 static int cortex_m3_clear_halt(target_t *target)
 {
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-	struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+	struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 
 	/* clear step if any */
 	cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
@@ -152,7 +152,7 @@ static int cortex_m3_clear_halt(target_t *target)
 static int cortex_m3_single_step_core(target_t *target)
 {
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-	struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+	struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 	uint32_t dhcsr_save;
 
 	/* backup dhcsr reg */
@@ -176,7 +176,7 @@ static int cortex_m3_endreset_event(target_t *target)
 	int i;
 	uint32_t dcb_demcr;
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-	struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+	struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 	cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
 	cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
 
@@ -260,7 +260,7 @@ static int cortex_m3_examine_exception_reason(target_t *target)
 {
 	uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
 	mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 	switch (armv7m->exception_number)
@@ -311,7 +311,7 @@ static int cortex_m3_debug_entry(target_t *target)
 	int retval;
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
 	struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
 	LOG_DEBUG(" ");
 
@@ -381,7 +381,7 @@ static int cortex_m3_poll(target_t *target)
 	int retval;
 	enum target_state prev_target_state = target->state;
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-	struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+	struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 
 	/* Read from Debug Halting Control and Status Register */
 	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -495,7 +495,7 @@ static int cortex_m3_halt(target_t *target)
 static int cortex_m3_soft_reset_halt(struct target_s *target)
 {
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-	struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+	struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 	uint32_t dcb_dhcsr = 0;
 	int retval, timeout = 0;
 
@@ -637,7 +637,7 @@ static int cortex_m3_step(struct target_s *target, int current,
 {
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
 	struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 	breakpoint_t *breakpoint = NULL;
 
 	if (target->state != TARGET_HALTED)
@@ -687,7 +687,7 @@ static int cortex_m3_step(struct target_s *target, int current,
 static int cortex_m3_assert_reset(target_t *target)
 {
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-	struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+	struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 	int assert_srst = 1;
 
 	LOG_DEBUG("target->state: %s",
@@ -1232,7 +1232,7 @@ static int cortex_m3_load_core_reg_u32(struct target_s *target,
 {
 	int retval;
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
 	/* NOTE:  we "know" here that the register identifiers used
 	 * in the v7m header match the Cortex-M3 Debug Core Register
@@ -1296,7 +1296,7 @@ static int cortex_m3_store_core_reg_u32(struct target_s *target,
 	int retval;
 	uint32_t reg;
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
 #ifdef ARMV7_GDB_HACKS
 	/* If the LR register is being modified, make sure it will put us
@@ -1371,7 +1371,7 @@ static int cortex_m3_read_memory(struct target_s *target, uint32_t address,
 		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 	int retval;
 
 	/* sanitize arguments */
@@ -1403,7 +1403,7 @@ static int cortex_m3_write_memory(struct target_s *target, uint32_t address,
 		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 	int retval;
 
 	/* sanitize arguments */
@@ -1588,7 +1588,7 @@ static int cortex_m3_examine(struct target_s *target)
 	uint32_t cpuid, fpcr;
 	int i;
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-	struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+	struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 
 	if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
 		return retval;
@@ -1630,7 +1630,7 @@ static int cortex_m3_examine(struct target_s *target)
 	return ERROR_OK;
 }
 
-static int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
 {
 	uint16_t dcrdr;
 
@@ -1655,7 +1655,7 @@ static int cortex_m3_target_request_data(target_t *target,
 		uint32_t size, uint8_t *buffer)
 {
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 	uint8_t data;
 	uint8_t ctrl;
 	uint32_t i;
@@ -1675,7 +1675,7 @@ static int cortex_m3_handle_target_request(void *priv)
 	if (!target_was_examined(target))
 		return ERROR_OK;
 	struct armv7m_common_s *armv7m = target_to_armv7m(target);
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
 	if (!target->dbg_msg_enabled)
 		return ERROR_OK;
@@ -1838,7 +1838,7 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
 	target_t *target = get_current_target(cmd_ctx);
 	struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
 	struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 	uint32_t demcr = 0;
 	int retval;
 	int i;