Move TCL script files -- Step 2 of 2:

- Move src/tcl to tcl/.
- Update top Makefile.am to use new path name.


git-svn-id: svn://svn.berlios.de/openocd/trunk@1919 b42882b7-edfa-0310-969c-e2dbd0fdcd60

31 files changed, 0 insertions, 1388 deletions

diff --git a/src/tcl/board/arm_evaluator7t.cfg b/src/tcl/board/arm_evaluator7t.cfg
deleted file mode 100644
index 9cca2391..00000000
--- a/src/tcl/board/arm_evaluator7t.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# This board is from ARM and has an samsung s3c45101x01 chip
-
-source [find target/samsung_s3c4510.cfg]
-
-# 
-# FIXME:
-#  Add (A) sdram configuration
-#  Add (B) flash cfi programing configuration
-#
-
diff --git a/src/tcl/board/at91rm9200-dk.cfg b/src/tcl/board/at91rm9200-dk.cfg
deleted file mode 100644
index 900ee351..00000000
--- a/src/tcl/board/at91rm9200-dk.cfg
+++ /dev/null
@@ -1,78 +0,0 @@
-#
-# This is for the "at91rm9200-DK" (not the EK) eval board.
-#
-# The two are probably very simular.... I have DK...
-#
-# It has atmel at91rm9200 chip.
-source [find target/at91rm9200.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash_bank cfi 0x10000000 0x00200000 2 2 0
-
-
-proc at91rm9200_dk_init { } {
-    # Try to run at 1khz... Yea, that slow!
-    # Chip is really running @ 32khz
-    jtag_khz 8
-    
-    mww 0xfffffc64 0xffffffff
-    ##  disable all clocks but system clock
-    mww 0xfffffc04 0xfffffffe
-    ##  disable all clocks to pioa and piob
-    mww 0xfffffc14 0xffffffc3
-    ##  master clock = slow cpu = slow
-    ##  (means the CPU is running at 32khz!)
-    mww 0xfffffc30 0
-    ##  main osc enable
-    mww 0xfffffc20 0x0000ff01
-    ##  program pllA
-    mww 0xfffffc28 0x20263e04
-    ##  program pllB
-    mww 0xfffffc2c 0x10483e0e
-    ##  let pll settle... sleep 100msec
-    sleep 100
-    ##  switch to fast clock
-    mww 0xfffffc30 0x202
-    ## Sleep some - (go read)
-    sleep 100
-    
-    #========================================
-    # CPU now runs at 180mhz
-    # SYS runs at 60mhz.
-    jtag_khz 40000
-    #========================================
-    
-    
-    ##  set memc for all memories
-    mww 0xffffff60 0x02
-    ##  program smc controller
-    mww 0xffffff70 0x3284
-    ##  init sdram
-    mww 0xffffff98 0x7fffffd0
-    ##  all banks precharge
-    mww 0xffffff80 0x02
-    ##  touch sdram chip to make it work
-    mww 0x20000000 0
-    ##  sdram controller mode register 
-    mww 0xffffff90 0x04
-    mww 0x20000000 0
-    mww 0x20000000 0
-    mww 0x20000000 0
-    mww 0x20000000 0
-    mww 0x20000000 0
-    mww 0x20000000 0
-    mww 0x20000000 0
-    mww 0x20000000 0
-    ##  sdram controller mode register
-    ##  Refresh, etc....
-    mww 0xffffff90 0x03
-    mww 0x20000080 0
-    mww 0xffffff94 0x1f4
-    mww 0x20000080 0
-    mww 0xffffff90 0x10
-    mww 0x20000000 0
-    mww 0xffffff00 0x01
-
-}
diff --git a/src/tcl/board/crossbow_tech_imote2.cfg b/src/tcl/board/crossbow_tech_imote2.cfg
deleted file mode 100644
index 7527bef8..00000000
--- a/src/tcl/board/crossbow_tech_imote2.cfg
+++ /dev/null
@@ -1,46 +0,0 @@
-# Crossbow Technology iMote2
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME imote2
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-   set  _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-  # force an error till we get a good number
-   set _CPUTAPID 0xffffffff
-}
-
-# PXA271 and an Intel Strataflash of 32 Megabytes (p30)
-# 
-# Marvell/Intel PXA270 Script
-# set jtag_nsrst_delay to the delay introduced by your reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_nsrst_delay 800 
-# set the jtag_ntrst_delay to the delay introduced by a reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_ntrst_delay 0
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst separate
-#jtag scan chain
-
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
-$_TARGETNAME configure -work-area-virt 0x0x5c000000 -work-area-phys 0x0x5c000000 -work-area-size 0x10000 -work-area-backup 1
-# maps to PXA internal RAM. If you are using a PXA255
-# you must initialize SDRAM or leave this option off
-
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-# works for P30 flash
-flash bank cfi 0x00000000 0x2000000 2 2 0
diff --git a/src/tcl/board/digi_connectcore_wi-9c.cfg b/src/tcl/board/digi_connectcore_wi-9c.cfg
deleted file mode 100644
index 93317327..00000000
--- a/src/tcl/board/digi_connectcore_wi-9c.cfg
+++ /dev/null
@@ -1,127 +0,0 @@
-######################################
-# Target: DIGI ConnectCore Wi-9C
-######################################
-
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME ns9360
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-  # This config file was defaulting to big endian..
-   set  _ENDIAN big
-}
-
-
-# What's a good fallback frequency for this board if RCLK is
-# not available??
-jtag_rclk 1000
-
-
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0xFFFFFFFF
-}
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 0
-
-
-######################
-# Target configuration
-######################
-
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-$_TARGETNAME configure -event reset-init {
-	mww 0x90600104 0x33313333
-	mww 0xA0700000 0x00000001  # Enable the memory controller.
-	mww 0xA0700024 0x00000006  # Set the refresh counter 6
-	mww 0xA0700028 0x00000001  # 
-	mww 0xA0700030 0x00000001  # Set the precharge period
-	mww 0xA0700034 0x00000004  # Active to precharge command period is 16 clock cycles
-	mww 0xA070003C 0x00000001  # tAPR
-	mww 0xA0700040 0x00000005  # tDAL
-	mww 0xA0700044 0x00000001  # tWR
-	mww 0xA0700048 0x00000006  # tRC 32 clock cycles  
-	mww 0xA070004C 0x00000006  # tRFC 32 clock cycles
-	mww 0xA0700054 0x00000001  # tRRD
-	mww 0xA0700058 0x00000001  # tMRD
-	mww 0xA0700100 0x00004280  # Dynamic Config 0 (cs4) 
-	mww 0xA0700120 0x00004280  # Dynamic Config 1 (cs5)
-	mww 0xA0700140 0x00004280  # Dynamic Config 2 (cs6)
-	mww 0xA0700160 0x00004280  # Dynamic Config 3 (cs7)
-	#
-	mww 0xA0700104 0x00000203  # CAS latency is 2 at 100 MHz
-	mww 0xA0700124 0x00000203  # CAS latency is 2 at 100 MHz
-	mww 0xA0700144 0x00000203  # CAS latency is 2 at 100 MHz
-	mww 0xA0700164 0x00000203  # CAS latency is 2 at 100 MHz
-	#
-	mww 0xA0700020 0x00000103  # issue SDRAM PALL command
-	#
-	mww 0xA0700024 0x00000001  # Set the refresh counter to be as small as possible
-	#
-	# Add some dummy writes to give the SDRAM time to settle, it needs two
-	# AHB clock cycles, here we poke in the debugger flag, this lets
-	# the software know that we are in the debugger
-	mww 0xA0900000 0x00000002
-	mww 0xA0900000 0x00000002
-	mww 0xA0900000 0x00000002
-	mww 0xA0900000 0x00000002
-	mww 0xA0900000 0x00000002
-	#
-	mdw 0xA0900000 
-	mdw 0xA0900000 
-	mdw 0xA0900000 
-	mdw 0xA0900000 
-	mdw 0xA0900000 
-	#
-	mww 0xA0700024 0x00000030 # Set the refresh counter to 30
-	mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
-	#
-	# Next we perform a read of RAM.
-	# mw = move word.
-	mdw 0x00022000
-	# mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3
-	#
-	mww 0xA0700020 0x00000003   # issue SDRAM NORMAL command
-	mww 0xA0700100 0x00084280   # Enable buffer access
-	mww 0xA0700120 0x00084280   # Enable buffer access
-	mww 0xA0700140 0x00084280   # Enable buffer access
-	mww 0xA0700160 0x00084280   # Enable buffer access
-
-	#Set byte lane state (static mem 1)"
-	mww 0xA0700220, 0x00000082
-	#Flash Start
-	mww 0xA09001F8, 0x50000000
-	#Flash Mask Reg
-	mww 0xA09001FC, 0xFF000001
-	mww 0xA0700028, 0x00000001
-
-	#  RAMAddr = 0x00020000
-	#  RAMSize = 0x00004000
-
-	# Set the processor mode
-	reg cpsr 0xd3
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
-
-#####################
-# Flash configuration
-#####################
-
-#M29DW323DB - not working
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x50000000 0x0400000 2 2 0
-
-
-
diff --git a/src/tcl/board/dm355evm.cfg b/src/tcl/board/dm355evm.cfg
deleted file mode 100644
index 9e6dc73b..00000000
--- a/src/tcl/board/dm355evm.cfg
+++ /dev/null
@@ -1,119 +0,0 @@
-#
-# DM355 EVM board
-#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
-#   http://c6000.spectrumdigital.com/evmdm355/
-
-source [find target/ti_dm355.cfg]
-
-reset_config trst_and_srst separate
-
-# NOTE:  disable or replace this call to dm355evm_init if you're
-# debugging new UBL code from SRAM.
-$_TARGETNAME configure -event reset-init { dm355evm_init }
-
-#
-# This post-reset init is called when the MMU isn't active, all IRQs
-# are disabled, etc.  It should do most of what a UBL does, except for
-# loading code (like U-Boot) into DRAM and running it.
-#
-proc dm355evm_init {} {
-	global dm355
-
-	puts "Initialize DM355 EVM board"
-
-	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
-	jtag_khz 1500
-
-	########################
-	# PLL1		= 432 MHz (/8, x144)
-	# ...SYSCLK1	= 216 MHz (/2)  ... ARM, MJCP
-	# ...SYSCLK2	= 108 MHz (/4)  ... Peripherals
-	# ...SYSCLK3	= 27  MHz (/16) ... VPBE, DAC
-	# ...SYSCLK4	= 108 MHz (/4)  ... VPSS
-	#	pll1.{prediv,div1,div2} are fixed
-	#	pll1.postdiv set in MISC (for *this* speed grade)
-
-	set addr [dict get $dm355 pllc1]
-	set pll_divs [dict create]
-	dict set pll_divs div3 16
-	dict set pll_divs div4 8
-	pll_setup $addr 144 $pll_divs
-
-	# ARM is now running at 216 MHz, so JTAG can go faster
-	jtag_khz 20000
-
-	########################
-	# PLL2		= 342 MHz (/8, x114)
-	# ....SYSCLK1	= 342 MHz (/1)  ... DDR PHY at 171 MHz, 2x clock
-	#	pll2.{postdiv,div1} are fixed
-
-	set addr [dict get $dm355 pllc2]
-	set pll_divs [dict create]
-	dict set pll_divs prediv 8
-	pll_setup $addr 114 $pll_divs
-
-	########################
-	# PINMUX
-
-	# All Video Inputs
-	davinci_pinmux $dm355 0 0x00007f55
-	# All Video Outputs
-	davinci_pinmux $dm355 1 0x00145555
-	# EMIFA (NOTE: more could be set up for use as GPIOs)
-	davinci_pinmux $dm355 2 0x00000c08
-	# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
-	davinci_pinmux $dm355 3 0x1bff55ff
-	# MMC/SD0 instead of MS; SPI0
-	davinci_pinmux $dm355 4 0x00000000
-
-	########################
-	# PSC setup (minimal)
-
-	# DDR EMIF/13, AEMIF/14, UART0/19
-	psc_enable 13
-	psc_enable 14
-	psc_enable 19
-	psc_go
-
-	########################
-	# DDR2 EMIF
-
-	# FIXME setup
-
-	########################
-	# ASYNC EMIF
-
-	set addr [dict get $dm355 a_emif]
-
-	# slow/pessimistic timings
-	set nand_timings 0x40400204
-	# fast (25% faster page reads)
-	#set nand_timings 0x0400008c
-
-	# AWCCR
-	mww [expr $addr + 0x04] 0xff
-	# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
-	mww [expr $addr + 0x10] $nand_timings
-	# CS1 == dm9000 Ethernet
-	mww [expr $addr + 0x14] 0x00a00505
-	# NANDFCR -- only CS0 has NAND
-	mww [expr $addr + 0x60] 0x01
-
-	########################
-	# UART0
-
-	# FIXME setup
-}
-
-# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
-#
-# NOTE:  "hwecc4" here presumes that if you're using the standard 2GB NAND
-# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
-# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
-# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
-nand device davinci 0 0x02000000 hwecc4 0x01e10000
-nand device davinci 0 0x02004000 hwecc4 0x01e10000
-
-# FIXME
-#  - support writing UBL with its header (new layout only with new ROMs)
-#  - support writing ABL/U-Boot with its header (new layout)
diff --git a/src/tcl/board/eir.cfg b/src/tcl/board/eir.cfg
deleted file mode 100644
index 08765658..00000000
--- a/src/tcl/board/eir.cfg
+++ /dev/null
@@ -1,94 +0,0 @@
-# Elector Internet Radio board
-# http://www.ethernut.de/en/hardware/eir/index.html
-
-source [find target/sam7se512.cfg]
-
-$_TARGETNAME configure -event reset-init {
-	# WDT_MR, disable watchdog 
-	mww 0xFFFFFD44 0x00008000
-
-	# RSTC_MR, enable user reset
-	mww 0xfffffd08 0xa5000001
-
-	# CKGR_MOR
-	mww 0xFFFFFC20 0x00000601
-	sleep 10
-
-	# CKGR_PLLR
-	mww 0xFFFFFC2C 0x00481c0e
-	sleep 10
-
-	# PMC_MCKR
-	mww 0xFFFFFC30 0x00000007
-	sleep 10
-
-	# PMC_IER
-	mww 0xFFFFFF60 0x00480100
-
-	#
-	# Enable SDRAM interface.
-	#
-
-	# Enable SDRAM control at PIO A.
-	mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
-	mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
-
-	# Enable address bus (A0, A2-A11, A13-A17) at PIO B
-	mww 0xfffff674 0x0003effd # PIO_BSR_OFF
-	mww 0xfffff604 0x0003effd # PIO_PDR_OFF
-
-	# Enable 16 bit data bus at PIO C
-	mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
-	mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
-
-	# Enable SDRAM chip select
-	mww 0xffffff80 0x00000002 # EBI_CSA_OFF
-
-	# Set SDRAM characteristics in configuration register.
-	# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
-	mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
-	sleep 10
-
-	# Issue 16 bit SDRAM command: NOP
-	mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-
-	# Issue 16 bit SDRAM command: Precharge all
-	mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-
-	# Issue 8 auto-refresh cycles
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-
-	# Issue 16 bit SDRAM command: Set mode register  
-	mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
-	mww 0x20000014 0xcafedede
-
-	# Set refresh rate count ???
-	mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
-
-	# Issue 16 bit SDRAM command: Normal mode
-	mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000180
-
-	#
-	# Enable external reset key.
-	#
-	mww 0xfffffd08 0xa5000001
-}
-
diff --git a/src/tcl/board/hammer.cfg b/src/tcl/board/hammer.cfg
deleted file mode 100644
index ed83803f..00000000
--- a/src/tcl/board/hammer.cfg
+++ /dev/null
@@ -1,36 +0,0 @@
-# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
-# http://www.tincantools.com
-
-source [find target/samsung_s3c2410.cfg]
-
-$_TARGETNAME configure -event reset-init {
-	# Reset Script for the TinCanTools S3C2410 Based Hammer Module
-	# http://www.tincantools.com
-	#
-	# Setup primary clocks and initialize the SDRAM
-	mww 0x53000000 0x00000000
-	mww 0x4a000008 0xffffffff
-	mww 0x4a00000c 0x000007ff
-	mww 0x4c000000 0x00ffffff
-	mww 0x4c000014 0x00000003
-	mww 0x4c000004 0x000a1031
-	mww 0x48000000 0x11111122
-	mww 0x48000004 0x00000700
-	mww 0x48000008 0x00000700
-	mww 0x4800000c 0x00000700
-	mww 0x48000010 0x00000700
-	mww 0x48000014 0x00000700
-	mww 0x48000018 0x00000700
-	mww 0x4800001c 0x00018005
-	mww 0x48000020 0x00018005
-	mww 0x48000024 0x009c0459
-	mww 0x48000028 0x000000b2
-	mww 0x4800002c 0x00000030
-	mww 0x48000030 0x00000030
-	flash probe 0
-}
-
-
-#flash configuration
-#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
-flash bank cfi 0x00000000 0x1000000 2 2 0
diff --git a/src/tcl/board/hitex_stm32-performancestick.cfg b/src/tcl/board/hitex_stm32-performancestick.cfg
deleted file mode 100644
index 5effbd96..00000000
--- a/src/tcl/board/hitex_stm32-performancestick.cfg
+++ /dev/null
@@ -1,50 +0,0 @@
-# Hitex stm32 performance stick
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME stm32_hitex
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-   set  _ENDIAN little
-}
-
-# set jtag speed
-jtag_khz 500
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-#jtag scan chain
-# The CPU
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-  # See STM Document RM0008
-  # Section 26.6.3
-   set _CPUTAPID 0x3ba00477
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# The boundery scan register, leave the "expected-id" undefined.
-jtag newtap $_CHIPNAME bs  -irlen 5 -ircapture 0x1 -irmask 0x1 
-
-# configure str750 connected to jtag chain
-jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-
-#
-flash bank stm32x 0 0 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/tcl/board/hitex_str9-comstick.cfg b/src/tcl/board/hitex_str9-comstick.cfg
deleted file mode 100644
index de4d56dd..00000000
--- a/src/tcl/board/hitex_str9-comstick.cfg
+++ /dev/null
@@ -1,72 +0,0 @@
-# Hitex STR9-comStick
-# http://www.hitex.com/index.php?id=383
-# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
-
-source [find interface/hitex_str9-comstick.cfg]
-
-# set jtag speed
-jtag_khz 3000
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-   set  _ENDIAN little
-}
-
-if { [info exists FLASHTAPID ] } {
-   set _FLASHTAPID $FLASHTAPID
-} else {
-   set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
-   set _BSTAPID $BSTAPID
-} else {
-   # Found on STR9-comStick, revision STR912CS-A1
-   set _BSTAPID1 0x1457f041
-   # Found on STR9-comStick, revision STR912CS-A2
-   set _BSTAPID2 0x2457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-
-$_TARGETNAME configure -event reset-init {
-	# We can increase speed now that we know the target is halted.
-	#jtag_rclk 3000
-	
-	# -- Enable 96K RAM
-	# PFQBC enabled / DTCM & AHB wait-states disabled
-	mww 0x5C002034 0x0191 
-
-	str9x flash_config 0 4 2 0 0x80000
-	flash protect 0 0 7 off
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
diff --git a/src/tcl/board/iar_str912_sk.cfg b/src/tcl/board/iar_str912_sk.cfg
deleted file mode 100644
index ba060a04..00000000
--- a/src/tcl/board/iar_str912_sk.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-# The IAR str912-sk evaluation kick start board has an str912
-
-source [find target/str912.cfg]
\ No newline at end of file
diff --git a/src/tcl/board/imx27ads.cfg b/src/tcl/board/imx27ads.cfg
deleted file mode 100644
index dc0de4a6..00000000
--- a/src/tcl/board/imx27ads.cfg
+++ /dev/null
@@ -1,75 +0,0 @@
-# The IMX27 ADS eval board has a single IMX27 chip
-# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
-source [find target/imx27.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { imx27ads_init }
-
-# The IMX27 ADS board has a NOR flash on CS0
-flash_bank cfi 0xc0000000 0x00200000 2 2 0
-
-proc imx27ads_init { } {
-	# This setup puts RAM at 0xA0000000
-
-	# reset the board correctly
-	reset run
-	reset halt
-
-	mww 0x10000000 0x20040304
-	mww 0x10020000 0x00000000
-	mww 0x10000004 0xDFFBFCFB
-	mww 0x10020004 0xFFFFFFFF
-
-	sleep 100
-
-	# ========================================
-	#  Configure DDR on CSD0 -- initial reset
-	# ========================================
-	mww 0xD8001010 0x00000008 
-
-	# ========================================
-	#  Configure PSRAM on CS5 
-	# ========================================
-	mww 0xd8002050 0x0000dcf6
-	mww 0xd8002054 0x444a4541 
-	mww 0xd8002058 0x44443302 
-
-	#  ========================================
-	#         Configure16 bit NorFlash on CS0
-	#  ========================================
-	mww 0xd8002000 0x0000CC03 
-	mww 0xd8002004 0xa0330D01 
-	mww 0xd8002008 0x00220800 
-
-	# ========================================
-	#  Configure CPLD on CS4 
-	# ========================================
-	mww 0xd8002040 0x0000DCF6 
-	mww 0xd8002044 0x444A4541 
-	mww 0xd8002048 0x44443302 
-
-	# ========================================
-	#  Configure DDR on CSD0 -- wait 5000 cycle 
-	# ========================================
-	mww 0x10027828 0x55555555 
-	mww 0x10027830 0x55555555 
-	mww 0x10027834 0x55555555 
-	mww 0x10027838 0x00005005 
-	mww 0x1002783C 0x15555555 
-
-	mww 0xD8001010 0x00000004 
-
-	mww 0xD8001004 0x00795729 
-
-	mww 0xD8001000 0x92200000 
-	mww 0xA0000F00 0x0
-
-	mww 0xD8001000 0xA2200000 
-	mww 0xA0000F00 0x0
-	mww 0xA0000F00 0x0
-
-	mww 0xD8001000 0xB2200000 
-	mwb 0xA0000033 0xFF
-	mwb 0xA1000000 0xAA
-
-	mww 0xD8001000 0x82228085 
-}
diff --git a/src/tcl/board/imx27lnst.cfg b/src/tcl/board/imx27lnst.cfg
deleted file mode 100644
index 2ee7f094..00000000
--- a/src/tcl/board/imx27lnst.cfg
+++ /dev/null
@@ -1,59 +0,0 @@
-# The Linuxstamp-mx27 is board has a single IMX27 chip
-# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
-source [find target/imx27.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { imx27lnst_init }
-
-proc imx27lnst_init { } {
-	# This setup puts RAM at 0xA0000000
-
-	# reset the board correctly
-	jtag_khz 500
-	reset run
-	reset halt
-
-	mww 0x10000000 0x20040304
-	mww 0x10020000 0x00000000
-	mww 0x10000004 0xDFFBFCFB
-	mww 0x10020004 0xFFFFFFFF
-
-	sleep 100
-
-	# ========================================
-	#  Configure DDR on CSD0 -- initial reset
-	# ========================================
-	mww 0xD8001010 0x00000008 
-
-	sleep 100
-
-	# ========================================
-	#  Configure DDR on CSD0 -- wait 5000 cycle 
-	# ========================================
-	mww 0x10027828 0x55555555 
-	mww 0x10027830 0x55555555 
-	mww 0x10027834 0x55555555 
-	mww 0x10027838 0x00005005 
-	mww 0x1002783C 0x15555555 
-
-	mww 0xD8001010 0x00000004 
-
-	mww 0xD8001004 0x00795729 
-
-	#mww 0xD8001000 0x92200000
-	mww 0xD8001000 0x91120000
-	mww 0xA0000F00 0x0
-
-	#mww 0xD8001000 0xA2200000 
-	mww 0xD8001000 0xA1120000
-	mww 0xA0000F00 0x0
-	mww 0xA0000F00 0x0
-
-	#mww 0xD8001000 0xB2200000 
-	mww 0xD8001000 0xB1120000
-	mwb 0xA0000033 0xFF
-	mwb 0xA1000000 0xAA
-
-	#mww 0xD8001000 0x82228085 
-	mww 0xD8001000 0x81128080
-
-}
diff --git a/src/tcl/board/imx31pdk.cfg b/src/tcl/board/imx31pdk.cfg
deleted file mode 100644
index 67233567..00000000
--- a/src/tcl/board/imx31pdk.cfg
+++ /dev/null
@@ -1,101 +0,0 @@
-# The IMX31PDK eval board has a single IMX31 chip
-source [find target/imx31.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { imx31pdk_init }
-
-proc imx31pdk_init { } {
-	# This setup puts RAM at 0x80000000
-
-	# reset the board correctly
-	reset run
-	reset halt
-
-	# ========================================
-	# Init CCM
-	# ========================================
-	mww 0x53FC0000 0x040
-	mww 0x53F80000 0x074B0B7D
-
-	sleep 100
-
-	# ========================================
-	# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
-	# ========================================
-	mww 0x53F80004 0xFF871D50
-	mww 0x53F80010 0x00271C1B
-
-	# ========================================
-	# Configure CPLD on CS5 
-	# ========================================
-	mww 0xb8002050 0x0000DCF6
-	mww 0xb8002054 0x444A4541
-	mww 0xb8002058 0x44443302
-
-	# ========================================
-	# SDCLK
-	# ========================================
-	mww 0x43FAC26C 0
-
-	# ========================================
-	# CAS
-	# ========================================
-	mww 0x43FAC270 0
-
-	# ========================================
-	# RAS
-	# ========================================
-	mww 0x43FAC274 0
-
-	# ========================================
-	# CS2 (CSD0)
-	# ========================================
-	mww 0x43FAC27C 0x1000
-
-	# ========================================
-	# DQM3
-	# ========================================
-	mww 0x43FAC284 0
-
-	# ========================================
-	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
-	# ========================================
-	mww 0x43FAC288 0
-	mww 0x43FAC28C 0
-	mww 0x43FAC290 0
-	mww 0x43FAC294 0
-	mww 0x43FAC298 0
-	mww 0x43FAC29C 0
-	mww 0x43FAC2A0 0
-	mww 0x43FAC2A4 0
-	mww 0x43FAC2A8 0
-	mww 0x43FAC2AC 0
-	mww 0x43FAC2B0 0
-	mww 0x43FAC2B4 0
-	mww 0x43FAC2B8 0
-	mww 0x43FAC2BC 0
-	mww 0x43FAC2C0 0
-	mww 0x43FAC2C4 0
-	mww 0x43FAC2C8 0
-	mww 0x43FAC2CC 0
-	mww 0x43FAC2D0 0
-	mww 0x43FAC2D4 0
-	mww 0x43FAC2D8 0
-	mww 0x43FAC2DC 0
-
-	# ========================================
-	# Initialization script for 32 bit DDR on MX31 PDK
-	# ========================================
-	mww 0xB8001010 0x00000004
-	mww 0xB8001004 0x006ac73a
-	mww 0xB8001000 0x92100000
-	mww 0x80000f00 0x12344321
-	mww 0xB8001000 0xa2100000
-	mww 0x80000000 0x12344321
-	mww 0x80000000 0x12344321
-	mww 0xB8001000 0xb2100000
-	mwb 0x80000033 0xda
-	mwb 0x81000000 0xff
-	mww 0xB8001000 0x82226080
-	mww 0x80000000 0xDEADBEEF
-	mww 0xB8001010 0x0000000c
-}
diff --git a/src/tcl/board/keil_mcb2140.cfg b/src/tcl/board/keil_mcb2140.cfg
deleted file mode 100644
index db81efad..00000000
--- a/src/tcl/board/keil_mcb2140.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Keil MCB2140 eval board
-#
-# http://www.keil.com/mcb2140/picture.asp
-#
-
-source [find target/lpc2148.cfg]
-
diff --git a/src/tcl/board/linksys_nslu2.cfg b/src/tcl/board/linksys_nslu2.cfg
deleted file mode 100644
index 52984107..00000000
--- a/src/tcl/board/linksys_nslu2.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# This is for the LinkSys (CISCO) NSLU2 board
-# It is an Intel XSCALE IXP420 CPU.
-
-source [find target/ixp42x.cfg]
-# The _TARGETNAME is set by the above.
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
-
diff --git a/src/tcl/board/logicpd_imx27.cfg b/src/tcl/board/logicpd_imx27.cfg
deleted file mode 100644
index b068f1a1..00000000
--- a/src/tcl/board/logicpd_imx27.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-# The LogicPD Eval IMX27 eval board has a single IMX27 chip
-source [find target/imx27.cfg]
-
-# The Logic PD board has a NOR flash on CS0
-flash_bank cfi 0xc0000000 0x00200000 2 2 0
-
-#
-# FIX ME, Add support to
-#
-# (A) hard reset the board.
-# (B) Initialize the SDRAM on the board
-#
diff --git a/src/tcl/board/olimex_LPC2378STK.cfg b/src/tcl/board/olimex_LPC2378STK.cfg
deleted file mode 100644
index a4b422dc..00000000
--- a/src/tcl/board/olimex_LPC2378STK.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#####################################################
-# Olimex LPC2378STK eval board
-#
-# http://olimex.com/dev/lpc-2378stk.html
-#
-# Author: Sten, debian@sansys-electronic.com
-#####################################################
-#
-
-source [find target/lpc2378.cfg]
-
diff --git a/src/tcl/board/olimex_lpc_h2148.cfg b/src/tcl/board/olimex_lpc_h2148.cfg
deleted file mode 100644
index 7833fdec..00000000
--- a/src/tcl/board/olimex_lpc_h2148.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Olimex LPC-H2148 eval board
-#
-# http://www.olimex.com/dev/lpc-h2148.html
-#
-
-source [find target/lpc2148.cfg]
-
diff --git a/src/tcl/board/olimex_sam7_ex256.cfg b/src/tcl/board/olimex_sam7_ex256.cfg
deleted file mode 100644
index 5f83629d..00000000
--- a/src/tcl/board/olimex_sam7_ex256.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
-
-source [find target/sam7x256.cfg]
-
diff --git a/src/tcl/board/olimex_sam9_l9260.cfg b/src/tcl/board/olimex_sam9_l9260.cfg
deleted file mode 100644
index fbd8f5c0..00000000
--- a/src/tcl/board/olimex_sam9_l9260.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-##
-# Olimex SAM9-L9260 board configuration file
-#
-# Date			Author			Change
-# ----			-----			-----
-# 17/Jan/2009	Dean Glazeski	Initial Creation
-#
-##
-
-source [find target/at91sam9260.cfg]
diff --git a/src/tcl/board/olimex_stm32_h103.cfg b/src/tcl/board/olimex_stm32_h103.cfg
deleted file mode 100644
index fadf1755..00000000
--- a/src/tcl/board/olimex_stm32_h103.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Olimex STM32-H103 eval board
-#
-# http://olimex.com/dev/stm32-h103.html
-#
-
-source [find target/stm32.cfg]
-
diff --git a/src/tcl/board/pic-p32mx.cfg b/src/tcl/board/pic-p32mx.cfg
deleted file mode 100644
index 412a5067..00000000
--- a/src/tcl/board/pic-p32mx.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# The Olimex PIC-P32MX has a PIC32MX
-
-set CPUTAPID 0x40916053
-source [find target/pic32mx.cfg]
-
-init
-flash probe 0
-flash probe 1
diff --git a/src/tcl/board/pxa255_sst.cfg b/src/tcl/board/pxa255_sst.cfg
deleted file mode 100644
index 37ff1a8b..00000000
--- a/src/tcl/board/pxa255_sst.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-# A PXA255 test board with SST 39LF400A flash
-#
-# At reset the memory map is as follows. Note that
-# the memory map changes later on as the application 
-# starts...
-#
-# RAM at 0x4000000
-# Flash at 0x00000000
-#
-source [find target/pxa255.cfg]
-# Target name is set by above
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
-# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
-flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
-
diff --git a/src/tcl/board/sheevaplug.cfg b/src/tcl/board/sheevaplug.cfg
deleted file mode 100644
index 6fe3ce3e..00000000
--- a/src/tcl/board/sheevaplug.cfg
+++ /dev/null
@@ -1,122 +0,0 @@
-# Marvell SheevaPlug 
-
-source [find interface/sheevaplug.cfg]
-source [find target/feroceon.cfg]
-
-$_TARGETNAME configure \
-	-work-area-phys 0x10000000 \
-	-work-area-size 65536 \
-	-work-area-backup 0
-
-arm7_9 dcc_downloads enable
-
-# this assumes the hardware default peripherals location before u-Boot moves it
-nand device orion 0 0xd8000000
-
-proc sheevaplug_init { } {
-
-	# We need to assert DBGRQ while holding nSRST down.
-	# However DBGACK will be set only when nSRST is released.
-	# Furthermore, the JTAG interface doesn't respond at all when
-	# the CPU is in the WFI (wait for interrupts) state, so it is
-	# possible that initial tap examination failed.  So let's
-	# re-examine the target again here when nSRST is asserted which
-	# should then succeed.
-	jtag_reset 0 1
-	feroceon.cpu arp_examine
-	halt 0
-	jtag_reset 0 0
-	wait_halt
-
-	arm926ejs cp15 0 0 1 0 0x00052078
-
-	mww 0xD0001400 0x43000C30 #  DDR SDRAM Configuration Register
-	mww 0xD0001404 0x39543000 #  Dunit Control Low Register
-	mww 0xD0001408 0x22125451 #  DDR SDRAM Timing (Low) Register
-	mww 0xD000140C 0x00000833 #  DDR SDRAM Timing (High) Register
-	mww 0xD0001410 0x000000CC #  DDR SDRAM Address Control Register
-	mww 0xD0001414 0x00000000 #  DDR SDRAM Open Pages Control Register
-	mww 0xD0001418 0x00000000 #  DDR SDRAM Operation Register
-	mww 0xD000141C 0x00000C52 #  DDR SDRAM Mode Register
-	mww 0xD0001420 0x00000042 #  DDR SDRAM Extended Mode Register
-	mww 0xD0001424 0x0000F17F #  Dunit Control High Register
-	mww 0xD0001428 0x00085520 #  Dunit Control High Register
-	mww 0xD000147c 0x00008552 #  Dunit Control High Register
-	mww 0xD0001504 0x0FFFFFF1 #  CS0n Size Register
-	mww 0xD0001508 0x10000000 #  CS1n Base Register
-	mww 0xD000150C 0x0FFFFFF5 #  CS1n Size Register
-	mww 0xD0001514 0x00000000 #  CS2n Size Register
-	mww 0xD000151C 0x00000000 #  CS3n Size Register
-	mww 0xD0001494 0x003C0000 #  DDR2 SDRAM ODT Control (Low) Register
-	mww 0xD0001498 0x00000000 #  DDR2 SDRAM ODT Control (High) REgister
-	mww 0xD000149C 0x0000F80F #  DDR2 Dunit ODT Control Register
-	mww 0xD0001480 0x00000001 #  DDR SDRAM Initialization Control Register
-	mww 0xD0020204 0x00000000 #  Main IRQ Interrupt Mask Register
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-
-	mww 0xD0010000 0x01111111 #  MPP  0 to 7
-	mww 0xD0010004 0x11113322 #  MPP  8 to 15
-	mww 0xD0010008 0x00001111 #  MPP 16 to 23
-
-	mww 0xD0010418 0x003E07CF #  NAND Read Parameters REgister
-	mww 0xD001041C 0x000F0F0F #  NAND Write Parameters Register
-	mww 0xD0010470 0x01C7D943 #  NAND Flash Control Register
-
-}
-
-proc sheevaplug_reflash_uboot { } {
-
-	# reflash the u-Boot binary and reboot into it
-	sheevaplug_init
-	nand probe 0
-	nand erase 0 0x0 0xa0000
-	nand write 0 uboot.bin 0 oob_softecc_kw
-	resume
-
-}
-
-proc sheevaplug_load_uboot { } {
-
-	# load u-Boot into RAM and execute it
-	sheevaplug_init
-	load_image uboot.elf
-	verify_image uboot.elf
-	resume 0x00600000
-
-}
-
diff --git a/src/tcl/board/stm3210e_eval.cfg b/src/tcl/board/stm3210e_eval.cfg
deleted file mode 100644
index ab2f64f0..00000000
--- a/src/tcl/board/stm3210e_eval.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-# This is an STM32 eval board with a single STM32F103ZET6 chip on it.
-
-source [find target/stm32.cfg]
diff --git a/src/tcl/board/stm32f10x_128k_eval.cfg b/src/tcl/board/stm32f10x_128k_eval.cfg
deleted file mode 100644
index ce073708..00000000
--- a/src/tcl/board/stm32f10x_128k_eval.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-# This is an STM32 eval board with a single STM32F103VBT6 chip on it.
-
-source [find target/stm32.cfg]
-
diff --git a/src/tcl/board/str910-eval.cfg b/src/tcl/board/str910-eval.cfg
deleted file mode 100644
index 10a2100b..00000000
--- a/src/tcl/board/str910-eval.cfg
+++ /dev/null
@@ -1,61 +0,0 @@
-# str910-eval eval board
-# 
-# Need reset scripts 
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-   set  _ENDIAN little
-}
-
-if { [info exists FLASHTAPID ] } {
-   set _FLASHTAPID $FLASHTAPID
-} else {
-   set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
-   set _BSTAPID $BSTAPID
-} else {
-   set _BSTAPID 0x1457f041
-}
-jtag newtap $_CHIPNAME bs    -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
-	# We can increase speed now that we know the target is halted.
-	#jtag_rclk 3000
-	
-	# -- Enable 96K RAM
-	# PFQBC enabled / DTCM & AHB wait-states disabled
-	mww 0x5C002034 0x0191 
-
-	str9x flash_config 0 4 2 0 0x80000
-	flash protect 0 0 7 off
-}
-
-#flash bank str9x <base> <size> 0 0 <target#> <variant>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/tcl/board/ti_beagleboard.cfg b/src/tcl/board/ti_beagleboard.cfg
deleted file mode 100644
index 170df460..00000000
--- a/src/tcl/board/ti_beagleboard.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-
-source [find target/omap3530.cfg]
-
-reset_config trst_and_srst
-jtag_reset 1 1
-sleep 10
-runtest 10
-jtag_reset 0 0
-
-endstate RUN/IDLE
-
-init
-
-omap3_dbginit
diff --git a/src/tcl/board/unknown-board-atmel-at91sam9260.cfg b/src/tcl/board/unknown-board-atmel-at91sam9260.cfg
deleted file mode 100644
index 4d69f0fd..00000000
--- a/src/tcl/board/unknown-board-atmel-at91sam9260.cfg
+++ /dev/null
@@ -1,82 +0,0 @@
-# Thanks to Pieter Conradie for this script! 
-# Target:    Atmel AT91SAM9260
-######################################
-
-# We add to the minimal configuration.
-source [find target/at91sam9260.cfg]
-
-######################
-# Target configuration
-######################
-
-$_TARGETNAME configure -event reset-init {
-	# at reset chip runs at 32khz
-	jtag_khz 8
-	mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
-	mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
-
-	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
-	sleep 20                          # wait 20 ms
-	mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
-	sleep 10                          # wait 10 ms
-	mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198,656MHz
-	sleep 20                          # wait 20 ms
-	mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler
-	sleep 10                          # wait 10 ms
-	mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected
-	sleep 10                          # wait 10 ms
-
-	# Now run at anything fast... ie: 10mhz!
-	jtag_khz 10000                    # Increase JTAG Speed to 6 MHz
-	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
-
-	mww 0xffffec00 0x01020102         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
-	mww 0xffffec04 0x09070806         # SMC_PULSE0
-	mww 0xffffec08 0x000d000b         # SMC_CYCLE0
-	mww 0xffffec0c 0x00001003         # SMC_MODE0
-
-	flash probe 0                     # Identify flash bank 0
-
-	mww 0xfffff870 0xffff0000         # PIO_ASR : Select peripheral function for D15..D31
-	mww 0xfffff804 0xffff0000         # PIO_PDR : Disable PIO function for D15..D31
-
-	mww 0xffffef1c 0x2                # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
-
-	#mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
-	mww 0xffffea08 0x85227254         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
-
-	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
-	mww 0x20000000 0
-	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
-	mww 0x20000000 0
-	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
-	mww 0x20000000 0
-	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
-	mww 0x20000000 0
-	mww 0xffffea04 0x5d2              # SDRAMC_TR : Set refresh timer count to 15us
-}
-
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 0
-
diff --git a/src/tcl/board/x300t.cfg b/src/tcl/board/x300t.cfg
deleted file mode 100644
index 985f44ed..00000000
--- a/src/tcl/board/x300t.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-# This is for the T-Home X300T / X301T IPTV box,
-# which are based on IPTV reference designs from Kiss/Cisco KMM-3***
-#
-# It has Sigma Designs SMP8634 chip.
-source [find target/smp8634.cfg]
-
-$_TARGETNAME configure -event reset-init { x300t_init }
-
-# 1MB CFI capable flash
-# flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank cfi 0xac000000 0x100000 2 2 0
-
-proc x300t_init { } {
-	# Setup SDRAM config and flash mapping
-	# initialize ram
-	mww 0xa003fffc 3
-	mww 0xa003fffc 2
-	mww 0xa0030000 0xE34111BA
-	mww 0xa003fffc 0xa4444
-	mww 0xa003fffc 0
-	
-	# remap boot vector in CPU local RAM
-	mww 0xa006f000 0x60000
-	
-	# map flash to CPU address space REG_BASE_cpu_block+CPU_remap4
-	mww 0x0006f010 0x48000000
-	
-	# map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS)
-	mww 0x00061ff0 0x48000000
-}
diff --git a/src/tcl/board/zy1000.cfg b/src/tcl/board/zy1000.cfg
deleted file mode 100644
index d8bb4650..00000000
--- a/src/tcl/board/zy1000.cfg
+++ /dev/null
@@ -1,110 +0,0 @@
-#Script for ZY1000
-
-#Atmel ties SRST & TRST together, at which point it makes
-#no sense to use TRST, but use TMS instead.
-#
-#The annoying thing with tying SRST & TRST together is that
-#there is no way to halt the CPU *before and during* the
-#SRST reset, which means that the CPU will run a number
-#of cycles before it can be halted(as much as milliseconds).
-reset_config srst_only srst_pulls_trst
-
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME zy1000
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-   set  _ENDIAN little
-}
-
- 
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x1f0f0f0f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-# at CPU CLK <32kHz this must be disabled
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
-$_TARGETNAME configure -event reset-init { 
-	# Set up chip selects & timings
-	mww 0xFFE00000 0x0100273D
-	mww 0xFFE00004 0x08002125
-	mww 0xFFEe0008 0x02002125
-	mww 0xFFE0000c 0x03002125
-	mww 0xFFE00010 0x40000000
-	mww 0xFFE00014 0x50000000
-	mww 0xFFE00018 0x60000000
-	mww 0xFFE0001c 0x70000000
-	mww 0xFFE00020 0x00000001
-	mww 0xFFE00024 0x00000000
-	
-	# remap  
-	mww 0xFFFFF124 0xFFFFFFFF  
-	mww 0xffff0010 0x100
-	mww 0xffff0034 0x100
-	
-	#disable 16x5x UART interrupts
-	mww 0x08020004 0
-}
-
-# required for usable performance. Used for lots of
-# other things than flash programming.
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
-
-jtag_khz 16000
-
-
-proc production_info {} {
-	return "Serial number is official MAC number. Format XXXXXXXXXXXX"
-}
-
-# There is no return value from this procedure. If it is
-# successful it does not throw an exception
-#
-# Progress messages are output via puts 
-proc production {firmwarefile serialnumber} {
-	if {[string length $serialnumber]!=12} {
-		puts "Invalid serial number"
-		return
-	}
-
-	puts "Power cycling target"
-	power off
-	sleep 3000
-	power on
-	sleep 1000
-	reset init
-	flash write_image erase $firmwarefile 0x1000000 bin
-	verify_image $firmwarefile 0x1000000 bin
-
-	# Big endian... weee!!!!
-	puts "Setting MAC number to $serialnumber"	
-	flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1
-	flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1
-	puts "Production successful"
-} 
-
-
-proc production_test {} {
-	power on
-	sleep 1000
-	target_request debugmsgs enable
-	reset run
-	sleep 25000
-	target_request debugmsgs disable
-	return "See IP address above..."
-}