src/helper/configuration.h

	- Log output handlers now get a "const char *line"
	- Added "const" to parameter.

src/helper/command.c
src/helper/command.h
	- New function:  'command_output_text()'
	- Log output handlers now get a "const char *line"
 
src/helper/options.c
	- Log output handlers now get a "const char *line"

src/server/telnet_server.c
	- DO not transmit NULL bytes via TELNET.
	- Log output handlers now get a "const char *line"
	
src/server/gdb_server.c
	- Log output handlers now get a "const char *line"
	
	*** THIS INCLUDES PORTIONS OF A PATCH FROM Oyvind sent 
	previously to the mailing list for TCL users try

src/target/target.c
	*** THIS INCLUDES PORTIONS OF A PATCH FROM Oyvind sent 
	previously to the mailing list for TCL users try
	
src/target/target.h
	*** THIS INCLUDES PORTIONS OF A PATCH FROM Oyvind sent 
	previously to the mailing list for TCL users try

src/openocd.c
    - **MAJOR** Work: New TCL/Jim function: mem2array
	- **MAJOR** Work: Redirect Tcl/Jim stdio output to remote users.
	- Previously: TCL output did not go to GDB.
	- Previously: TCL output did not go to TELNET
	- Previously: TCL output only goes to control console.
	- This fixes that problem.
	+ Created callbacks:
		+openocd_jim_fwrite()	
		+openocd_jim_fread()
		+openocd_jim_vfprintf()
		+openocd_jim_fflush()
		+openocd_jim_fgets()

src/Makefile.am
	- New TCL files.
	- Future note: This should be more automated.  As the list of
	  'tcl' files grows maintaning this list will suck.

src/Jim.c
	- ** THIS INCLUDES A PREVIOUS PATCH I SENT EARLIER **
	- that impliments many [format] specifies JIM did not support.
	- Jim_FormatString() - **MAJOR** work.
	- Previously only supported "%s" "%d" and "%c"
	- And what support existed had bugs.
	- NEW: *MANY* formating parameters are now supported.
	- TODO: The "precision" specifier is not supported.

	** NEW ** This patch.
	
	- Jim_StringToWide() test if no conversion occured.
	- Jim_StringToIndex() test if no conversion occured.
	- Jim_StringToDouble() test if no conversion occured.

	** NEW ** This Patch. Major Work.
	- Previously output from JIM did not get sent to GDB
	- Ditto: Output to Telnet session.
	- Above items are now fixed - By introducing callbacks
	  new function pointers in the "interp" structure.

	- Helpers that call the callbacks.
	
	- New function: Jim_fprintf()
	- New function: Jim_vfprintf()
	- New function: Jim_fwrite()
	- New function: Jim_fread()
	- New function: Jim_fflush()
	- New function: Jim_fgets()

	By default: the output is to STDIO as previous.
	The "openocd.c" - redirects the output as needed.
	
	- Jim_Panic() - Send panic to both STDERR and the interps
	specified STDERR output as a 2nd choice.

	- Now JIM's "stdin/stdout/stderr" paramters are "void *"
	and are no longer "FILE *".

src/Jim.h
	- **MAJOR**
	-  New JIM STDIO callbacks in the "interp" structure.
	-  change: "stdin/stdout/stderr" are now "void *" cookies.
	-  New JIM stdio helper functions.



git-svn-id: svn://svn.berlios.de/openocd/trunk@755 b42882b7-edfa-0310-969c-e2dbd0fdcd60

6 files changed, 561 insertions, 0 deletions

diff --git a/src/tcl/chip/atmel/at91/aic.tcl b/src/tcl/chip/atmel/at91/aic.tcl
new file mode 100644
index 00000000..245224a5
--- /dev/null
+++ b/src/tcl/chip/atmel/at91/aic.tcl
@@ -0,0 +1,101 @@
+set AIC_SMR      	[expr $AT91C_BASE_AIC + 0x00000000 ]
+global AIC_SMR
+set AIC_SVR      	[expr $AT91C_BASE_AIC + 0x00000080 ]
+global AIC_SVR
+set AIC_IVR      	[expr $AT91C_BASE_AIC + 0x00000100 ]
+global AIC_IVR
+set AIC_FVR      	[expr $AT91C_BASE_AIC + 0x00000104 ]
+global AIC_FVR
+set AIC_ISR      	[expr $AT91C_BASE_AIC + 0x00000108 ]
+global AIC_ISR
+set AIC_IPR      	[expr $AT91C_BASE_AIC + 0x0000010C ]
+global AIC_IPR
+set AIC_IMR      	[expr $AT91C_BASE_AIC + 0x00000110 ]
+global AIC_IMR
+set AIC_CISR     	[expr $AT91C_BASE_AIC + 0x00000114 ]
+global AIC_CISR
+set AIC_IECR     	[expr $AT91C_BASE_AIC + 0x00000120 ]
+global AIC_IECR
+set AIC_IDCR     	[expr $AT91C_BASE_AIC + 0x00000124 ]
+global AIC_IDCR
+set AIC_ICCR     	[expr $AT91C_BASE_AIC + 0x00000128 ]
+global AIC_ICCR
+set AIC_ISCR     	[expr $AT91C_BASE_AIC + 0x0000012C ]
+global AIC_ISCR
+set AIC_EOICR    	[expr $AT91C_BASE_AIC + 0x00000130 ]
+global AIC_EOICR
+set AIC_SPU      	[expr $AT91C_BASE_AIC + 0x00000134 ]
+global AIC_SPU
+set AIC_DCR      	[expr $AT91C_BASE_AIC + 0x00000138 ]
+global AIC_DCR
+set AIC_FFER     	[expr $AT91C_BASE_AIC + 0x00000140 ]
+global AIC_FFER
+set AIC_FFDR     	[expr $AT91C_BASE_AIC + 0x00000144 ]
+global AIC_FFDR
+set AIC_FFSR     	[expr $AT91C_BASE_AIC + 0x00000148 ]
+global AIC_FFSR
+
+
+proc aic_enable_disable_list { VAL ENAME DNAME } {
+    global AT91C_ID
+
+    show_mmr32_bits AT91C_ID $VAL
+
+}
+
+proc show_AIC_IPR_helper { NAME ADDR VAL } {
+    aic_enable_disable_list  $VAL "IRQ PENDING" "irq not-pending"
+}
+
+proc show_AIC_IMR_helper { NAME ADDR VAL } {
+    aic_enable_disable_list  $VAL "IRQ ENABLED" "irq disabled"
+}
+
+
+proc show_AIC { } {
+    global AIC_SMR
+    if [catch { mem2array aaa 32 $AIC_SMR [expr 32 * 4] } msg ] {
+	error [format "%s (%s)" $msg AIC_SMR]
+    }
+    puts "AIC_SMR: Mode & Type"
+    global AT91C_ID
+    for { set x 0 } { $x < 32 } {  } {
+	puts -nonewline "   "
+	puts -nonewline [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	incr x
+	puts -nonewline [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	incr x
+	puts -nonewline [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	incr x
+	puts  [format "%2d: %5s 0x%08x"  $x $AT91C_ID($x) $aaa($x)]
+	incr x
+    }
+    global AIC_SVR
+    if [catch { mem2array aaa 32 $AIC_SVR [expr 32 * 4] } msg ] {
+	error [format "%s (%s)" $msg AIC_SVR]
+    }
+    puts "AIC_SVR: Vectors"
+    for { set x 0 } { $x < 32 } {  } {
+	puts -nonewline "   "
+	puts -nonewline [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	incr x
+	puts -nonewline [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	incr x
+	puts -nonewline [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	incr x
+	puts [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
+	incr x
+    } 
+
+    foreach REG {
+	AIC_IVR   AIC_FVR  AIC_ISR 
+	AIC_IPR  AIC_IMR  AIC_CISR  AIC_IECR AIC_IDCR
+	AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU  AIC_DCR     
+	AIC_FFER AIC_FFDR AIC_FFSR } {
+	if [catch { show_mmr32_reg $REG } msg ] {
+	    error $msg
+	    break
+	}
+    }
+}
+
diff --git a/src/tcl/chip/atmel/at91/at91sam7x128.tcl b/src/tcl/chip/atmel/at91/at91sam7x128.tcl
new file mode 100644
index 00000000..1cf7c1cf
--- /dev/null
+++ b/src/tcl/chip/atmel/at91/at91sam7x128.tcl
@@ -0,0 +1,128 @@
+source [find tcl/bitsbytes.tcl]
+source [find tcl/cpu/arm/arm7tdmi.tcl]
+source [find tcl/memory.tcl]
+source [find tcl/mmr_helpers.tcl]
+
+set CHIP_MAKER  atmel
+set CHIP_FAMILY at91sam7
+set CHIP_NAME   at91sam7x128
+# how many flash regions.
+set N_FLASH                1
+set FLASH(0,CHIPSELECT)    -1
+set FLASH(0,BASE)          0x00100000
+set FLASH(0,LEN)           $__128K
+set FLASH(0,HUMAN)         "internal flash"
+set FLASH(0,TYPE)          "flash"
+set FLASH(0,RWX)           $RWX_R_X
+set FLASH(0,ACCESS_WIDTH)  $ACCESS_WIDTH_ANY
+# how many ram regions.
+set N_RAM                  1
+set RAM(0,CHIPSELECT)      -1
+set RAM(0,BASE)            0x00200000
+set RAM(0,LEN)             $__32K
+set RAM(0,HUMAN)           "internal ram"
+set RAM(0,TYPE)            "ram"
+set RAM(0,RWX)             $RWX_RWX
+set RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# I AM LAZY... I create 1 region for all MMRs.
+set N_MMREGS    1
+set MMREGS(0,CHIPSELECT)      -1
+set MMREGS(0,BASE)            0xfff00000
+set MMREGS(0,LEN)             0x000fffff
+set MMREGS(0,HUMAN)           "mm-regs"
+set MMREGS(0,TYPE)            "mmr"
+set MMREGS(0,RWX)             $RWX_RW
+set MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# no external memory
+set N_XMEM 0
+
+
+
+
+set AT91C_BASE_SYS       0xFFFFF000
+set AT91C_BASE_AIC       0xFFFFF000
+set AT91C_BASE_PDC_DBGU  0xFFFFF300
+set AT91C_BASE_DBGU      0xFFFFF200
+set AT91C_BASE_PIOA      0xFFFFF400
+set AT91C_BASE_PIOB      0xFFFFF600
+set AT91C_BASE_CKGR      0xFFFFFC20
+set AT91C_BASE_PMC       0xFFFFFC00
+set AT91C_BASE_RSTC      0xFFFFFD00
+set AT91C_BASE_RTTC      0xFFFFFD20
+set AT91C_BASE_PITC      0xFFFFFD30
+set AT91C_BASE_WDTC      0xFFFFFD40
+set AT91C_BASE_VREG      0xFFFFFD60
+set AT91C_BASE_MC        0xFFFFFF00
+set AT91C_BASE_PDC_SPI1  0xFFFE4100
+set AT91C_BASE_SPI1      0xFFFE4000
+set AT91C_BASE_PDC_SPI0  0xFFFE0100
+set AT91C_BASE_SPI0      0xFFFE0000
+set AT91C_BASE_PDC_US1   0xFFFC4100
+set AT91C_BASE_US1       0xFFFC4000
+set AT91C_BASE_PDC_US0   0xFFFC0100
+set AT91C_BASE_US0       0xFFFC0000
+set AT91C_BASE_PDC_SSC   0xFFFD4100
+set AT91C_BASE_SSC       0xFFFD4000
+set AT91C_BASE_TWI       0xFFFB8000
+set AT91C_BASE_PWMC_CH3  0xFFFCC260
+set AT91C_BASE_PWMC_CH2  0xFFFCC240
+set AT91C_BASE_PWMC_CH1  0xFFFCC220
+set AT91C_BASE_PWMC_CH0  0xFFFCC200
+set AT91C_BASE_PWMC      0xFFFCC000
+set AT91C_BASE_UDP       0xFFFB0000
+set AT91C_BASE_TC0       0xFFFA0000
+set AT91C_BASE_TC1       0xFFFA0040
+set AT91C_BASE_TC2       0xFFFA0080
+set AT91C_BASE_TCB       0xFFFA0000
+set AT91C_BASE_CAN_MB0   0xFFFD0200
+set AT91C_BASE_CAN_MB1   0xFFFD0220
+set AT91C_BASE_CAN_MB2   0xFFFD0240
+set AT91C_BASE_CAN_MB3   0xFFFD0260
+set AT91C_BASE_CAN_MB4   0xFFFD0280
+set AT91C_BASE_CAN_MB5   0xFFFD02A0
+set AT91C_BASE_CAN_MB6   0xFFFD02C0
+set AT91C_BASE_CAN_MB7   0xFFFD02E0
+set AT91C_BASE_CAN       0xFFFD0000
+set AT91C_BASE_EMAC      0xFFFDC000
+set AT91C_BASE_PDC_ADC   0xFFFD8100
+set AT91C_BASE_ADC       0xFFFD8000
+
+set AT91C_ID(0) FIQ
+set AT91C_ID(1) SYS
+set AT91C_ID(2) PIOA
+set AT91C_ID(3) PIOB
+set AT91C_ID(4) SPI0
+set AT91C_ID(5) SPI1
+set AT91C_ID(6) US0
+set AT91C_ID(7) US1
+set AT91C_ID(8) SSC
+set AT91C_ID(9) TWI
+set AT91C_ID(10) PWMC
+set AT91C_ID(11) UDP
+set AT91C_ID(12) TC0
+set AT91C_ID(13) TC1
+set AT91C_ID(14) TC2
+set AT91C_ID(15) CAN
+set AT91C_ID(16) EMAC
+set AT91C_ID(17) ADC
+set AT91C_ID(18) ""
+set AT91C_ID(19) ""
+set AT91C_ID(20) ""
+set AT91C_ID(21) ""
+set AT91C_ID(22) ""
+set AT91C_ID(23) ""
+set AT91C_ID(24) ""
+set AT91C_ID(25) ""
+set AT91C_ID(26) ""
+set AT91C_ID(27) ""
+set AT91C_ID(28) ""
+set AT91C_ID(29) ""
+set AT91C_ID(30) IRQ0
+set AT91C_ID(31) IRQ1
+
+source [find tcl/chip/atmel/at91/aic.tcl]
+source [find tcl/chip/atmel/at91/usarts.tcl]
+source [find tcl/chip/atmel/at91/pmc.tcl]
+source [find tcl/chip/atmel/at91/rtt.tcl]
diff --git a/src/tcl/chip/atmel/at91/at91sam7x256.tcl b/src/tcl/chip/atmel/at91/at91sam7x256.tcl
new file mode 100644
index 00000000..1cba4859
--- /dev/null
+++ b/src/tcl/chip/atmel/at91/at91sam7x256.tcl
@@ -0,0 +1,126 @@
+source [find tcl/bitsbytes.tcl]
+source [find tcl/cpu/arm/arm7tdmi.tcl]
+source [find tcl/memory.tcl]
+source [find tcl/mmr_helpers.tcl]
+
+set CHIP_MAKER  atmel
+set CHIP_FAMILY at91sam7
+set CHIP_NAME   at91sam7x256
+# how many flash regions.
+set N_FLASH                1
+set FLASH(0,CHIPSELECT)    -1
+set FLASH(0,BASE)          0x00100000
+set FLASH(0,LEN)           $__256K
+set FLASH(0,HUMAN)         "internal flash"
+set FLASH(0,TYPE)          "flash"
+set FLASH(0,RWX)           $RWX_R_X
+set FLASH(0,ACCESS_WIDTH)  $ACCESS_WIDTH_ANY
+# how many ram regions.
+set N_RAM                  1
+set RAM(0,CHIPSELECT)      -1
+set RAM(0,BASE)            0x00200000
+set RAM(0,LEN)             $__64K
+set RAM(0,HUMAN)           "internal ram"
+set RAM(0,TYPE)            "ram"
+set RAM(0,RWX)             $RWX_RWX
+set RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# I AM LAZY... I create 1 region for all MMRs.
+set N_MMREGS    1
+set MMREGS(0,CHIPSELECT)      -1
+set MMREGS(0,BASE)            0xfff00000
+set MMREGS(0,LEN)             0x000fffff
+set MMREGS(0,HUMAN)           "mm-regs"
+set MMREGS(0,TYPE)            "mmr"
+set MMREGS(0,RWX)             $RWX_RW
+set MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# no external memory
+set N_XMEM 0
+
+set  AT91C_BASE_SYS              0xFFFFF000
+set  AT91C_BASE_AIC              0xFFFFF000
+set  AT91C_BASE_PDC_DBGU         0xFFFFF300
+set  AT91C_BASE_DBGU             0xFFFFF200
+set  AT91C_BASE_PIOA             0xFFFFF400
+set  AT91C_BASE_PIOB             0xFFFFF600
+set  AT91C_BASE_CKGR             0xFFFFFC20
+set  AT91C_BASE_PMC              0xFFFFFC00
+set  AT91C_BASE_RSTC             0xFFFFFD00
+set  AT91C_BASE_RTTC             0xFFFFFD20
+set  AT91C_BASE_PITC             0xFFFFFD30
+set  AT91C_BASE_WDTC             0xFFFFFD40
+set  AT91C_BASE_VREG             0xFFFFFD60
+set  AT91C_BASE_MC          0xFFFFFF00
+set  AT91C_BASE_PDC_SPI1      0xFFFE4100
+set  AT91C_BASE_SPI1          0xFFFE4000
+set  AT91C_BASE_PDC_SPI0      0xFFFE0100
+set  AT91C_BASE_SPI0          0xFFFE0000
+set  AT91C_BASE_PDC_US1       0xFFFC4100
+set  AT91C_BASE_US1           0xFFFC4000
+set  AT91C_BASE_PDC_US0       0xFFFC0100
+set  AT91C_BASE_US0           0xFFFC0000
+set  AT91C_BASE_PDC_SSC       0xFFFD4100
+set  AT91C_BASE_SSC           0xFFFD4000
+set  AT91C_BASE_TWI           0xFFFB8000
+set  AT91C_BASE_PWMC_CH3      0xFFFCC260
+set  AT91C_BASE_PWMC_CH2      0xFFFCC240
+set  AT91C_BASE_PWMC_CH1      0xFFFCC220
+set  AT91C_BASE_PWMC_CH0      0xFFFCC200
+set  AT91C_BASE_PWMC          0xFFFCC000
+set  AT91C_BASE_UDP           0xFFFB0000
+set  AT91C_BASE_TC0         0xFFFA0000
+set  AT91C_BASE_TC1         0xFFFA0040
+set  AT91C_BASE_TC2         0xFFFA0080
+set  AT91C_BASE_TCB             0xFFFA0000
+set  AT91C_BASE_CAN_MB0         0xFFFD0200
+set  AT91C_BASE_CAN_MB1         0xFFFD0220
+set  AT91C_BASE_CAN_MB2         0xFFFD0240
+set  AT91C_BASE_CAN_MB3         0xFFFD0260
+set  AT91C_BASE_CAN_MB4         0xFFFD0280
+set  AT91C_BASE_CAN_MB5         0xFFFD02A0
+set  AT91C_BASE_CAN_MB6         0xFFFD02C0
+set  AT91C_BASE_CAN_MB7         0xFFFD02E0
+set  AT91C_BASE_CAN             0xFFFD0000
+set  AT91C_BASE_EMAC            0xFFFDC000
+set  AT91C_BASE_PDC_ADC         0xFFFD8100
+set  AT91C_BASE_ADC             0xFFFD8000
+
+set AT91C_ID(0)   "FIQ"
+set AT91C_ID(1)   "SYS"
+set AT91C_ID(2)   "PIOA"
+set AT91C_ID(3)   "PIOB"
+set AT91C_ID(4)   "SPI0"
+set AT91C_ID(5)   "SPI1"
+set AT91C_ID(6)   "US0"
+set AT91C_ID(7)   "US1"
+set AT91C_ID(8)   "SSC"
+set AT91C_ID(9)   "TWI"
+set AT91C_ID(10)   "PWMC"
+set AT91C_ID(11)   "UDP"
+set AT91C_ID(12)   "TC0"
+set AT91C_ID(13)   "TC1"
+set AT91C_ID(14)   "TC2"
+set AT91C_ID(15)   "CAN"
+set AT91C_ID(16)   "EMAC"
+set AT91C_ID(17)   "ADC"
+set AT91C_ID(18)   ""
+set AT91C_ID(19)   ""
+set AT91C_ID(20)   ""
+set AT91C_ID(21)   ""
+set AT91C_ID(22)   ""
+set AT91C_ID(23)   ""
+set AT91C_ID(24)   ""
+set AT91C_ID(25)   ""
+set AT91C_ID(26)   ""
+set AT91C_ID(27)   ""
+set AT91C_ID(28)   ""
+set AT91C_ID(29)   ""
+set AT91C_ID(30)   "IRQ0"
+set AT91C_ID(31)   "IRQ1"
+
+
+source [find tcl/chip/atmel/at91/aic.tcl]
+source [find tcl/chip/atmel/at91/usarts.tcl]
+source [find tcl/chip/atmel/at91/pmc.tcl]
+source [find tcl/chip/atmel/at91/rtt.tcl]
diff --git a/src/tcl/chip/atmel/at91/pmc.tcl b/src/tcl/chip/atmel/at91/pmc.tcl
new file mode 100644
index 00000000..584acb80
--- /dev/null
+++ b/src/tcl/chip/atmel/at91/pmc.tcl
@@ -0,0 +1,17 @@
+
+if [info exists AT91C_MAINOSC_FREQ] {
+    # user set this... let it be.
+} {
+    # 18.432mhz is a common thing...
+    set AT91C_MAINOSC_FREQ 18432000
+}
+global AT91C_MAINOSC_FREQ
+
+if [info exists AT91C_SLOWOSC_FREQ] {
+    # user set this... let it be.
+} {
+    # 32khz is the norm
+    set AT91C_SLOWOSC_FREQ 32768
+}
+global AT91C_SLOWOSC_FREQ
+
diff --git a/src/tcl/chip/atmel/at91/rtt.tcl b/src/tcl/chip/atmel/at91/rtt.tcl
new file mode 100644
index 00000000..56abb29e
--- /dev/null
+++ b/src/tcl/chip/atmel/at91/rtt.tcl
@@ -0,0 +1,54 @@
+
+set RTTC_RTMR [expr $AT91C_BASE_RTTC + 0x00]
+set RTTC_RTAR [expr $AT91C_BASE_RTTC + 0x04]
+set RTTC_RTVR [expr $AT91C_BASE_RTTC + 0x08]
+set RTTC_RTSR [expr $AT91C_BASE_RTTC + 0x0c]
+global RTTC_RTMR
+global RTTC_RTAR
+global RTTC_RTVR
+global RTTC_RTSR
+
+proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
+    set rtpres [expr $VAL & 0x0ffff]
+    global BIT16 BIT17
+    if { $rtpres == 0 } {
+	set rtpres 65536;
+    } 
+    global AT91C_SLOWOSC_FREQ
+    set f [expr double($AT91C_SLOWOSC_FREQ) / double($rtpres)]
+    puts [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f]
+    if { $VAL & $BIT16 } {
+	puts "\tBit16 -> Alarm IRQ Enabled"
+    } else {
+	puts "\tBit16 -> Alarm IRQ Disabled"
+    }
+    if { $VAL & $BIT17 } {
+	puts "\tBit17 -> RTC Inc IRQ Enabled"
+    } else {
+	puts "\tBit17 -> RTC Inc IRQ Disabled"
+    }
+    # Bit 18 is write only.
+}
+
+proc show_RTTC_RTSR_helper { NAME ADDR VAL } {
+    global BIT0 BIT1
+    if { $VAL & $BIT0 } {
+	puts "\tBit0 -> ALARM PENDING"
+    } else {
+	puts "\tBit0 -> alarm not pending"
+    }
+    if { $VAL & $BIT1 } {
+	puts "\tBit0 -> RTINC PENDING"
+    } else {
+	puts "\tBit0 -> rtinc not pending"
+    }
+}
+
+proc show_RTTC { } {
+    
+    show_mmr32_reg RTTC_RTMR
+    show_mmr32_reg RTTC_RTAR
+    show_mmr32_reg RTTC_RTVR
+    show_mmr32_reg RTTC_RTSR
+}
+
diff --git a/src/tcl/chip/atmel/at91/usarts.tcl b/src/tcl/chip/atmel/at91/usarts.tcl
new file mode 100644
index 00000000..19f4ed4c
--- /dev/null
+++ b/src/tcl/chip/atmel/at91/usarts.tcl
@@ -0,0 +1,135 @@
+# the DBGU and USARTs are 'almost' indentical'
+set DBGU_CR         [expr $AT91C_BASE_DBGU + 0x00000000]
+set DBGU_MR         [expr $AT91C_BASE_DBGU + 0x00000004]
+set DBGU_IER        [expr $AT91C_BASE_DBGU + 0x00000008]
+set DBGU_IDR        [expr $AT91C_BASE_DBGU + 0x0000000C]
+set DBGU_IMR        [expr $AT91C_BASE_DBGU + 0x00000010]
+set DBGU_CSR        [expr $AT91C_BASE_DBGU + 0x00000014]
+set DBGU_RHR        [expr $AT91C_BASE_DBGU + 0x00000018]
+set DBGU_THR        [expr $AT91C_BASE_DBGU + 0x0000001C]
+set DBGU_BRGR       [expr $AT91C_BASE_DBGU + 0x00000020]
+# no RTOR
+# no TTGR
+# no FIDI
+# no NER
+set DBGU_CIDR       [expr $AT91C_BASE_DBGU + 0x00000040]
+set DBGU_EXID       [expr $AT91C_BASE_DBGU + 0x00000044]
+set DBGU_FNTR       [expr $AT91C_BASE_DBGU + 0x00000048]
+
+
+set USx_CR           0x00000000
+set USx_MR           0x00000004
+set USx_IER          0x00000008
+set USx_IDR          0x0000000C
+set USx_IMR          0x00000010
+set USx_CSR          0x00000014
+set USx_RHR          0x00000018
+set USx_THR          0x0000001C
+set USx_BRGR         0x00000020
+set USx_RTOR         0x00000024
+set USx_TTGR         0x00000028
+set USx_FIDI         0x00000040
+set USx_NER          0x00000044
+set USx_IF           0x0000004C
+
+# Create all the uarts that exist..
+# we blow up if there are >9
+
+
+proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
+    # First - just print it
+
+    set x [show_normalize_bitfield $VAL 3 0]
+    if { $x == 0 } {
+	puts "\tNormal operation"
+    } else {
+	puts [format "\tNon Normal operation mode: 0x%02x" $x]
+    }
+
+    set x [show_normalize_bitfield $VAL 11 9]
+    set s "unknown"
+    switch -exact $x { 
+	0 { set s "Even" }
+	1 { set s "Odd" }
+	2 { set s "Force=0" }
+	3 { set s "Force=1" }
+	* {
+	    set $x [expr $x & 6]
+	    switch -exact $x {
+		4 { set s "None" }
+		6 { set s "Multidrop Mode" }
+	    }
+	}
+    }
+    puts [format "\tParity: %s " $s]
+    
+    set x [expr 5 + [show_normalize_bitfield $VAL 7 6]]
+    puts [format "\tDatabits: %d" $x]
+
+    set x [show_normalize_bitfield $VAL 13 12]
+    switch -exact $x {
+	0 { puts "\tStop bits: 1" }
+	1 { puts "\tStop bits: 1.5" }
+	2 { puts "\tStop bits: 2" }
+	3 { puts "\tStop bits: Illegal/Reserved" }
+    }
+}
+
+# For every possbile usart...
+foreach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } {
+    set n AT91C_BASE_[set WHO]
+    set str ""
+
+    # Only if it exists on the chip 
+    if [ info exists $n ] {
+	# Hence: $n - is like AT91C_BASE_USx
+	# For every sub-register
+	foreach REG {CR MR IER IDR IMR CSR RHR THR BRGR RTOR TTGR FIDI NER IF}	{
+	    # vn = variable name
+	    set vn [set WHO]_[set REG]
+	    # vn = USx_IER
+	    # vv = variable value
+	    set vv [expr $$n + [set USx_[set REG]]]
+	    # And VV is the address in memory of that register
+
+
+	    # make that VN a GLOBAL so others can find it
+	    global $vn
+	    set $vn $vv
+
+	    # Create a command for this specific register.
+	    proc show_$vn { } "show_mmr32_reg $vn"
+
+	    # Add this command to the Device(as a whole) command
+	    set str "$str\nshow_$vn"
+	}
+	# Now - create the DEVICE(as a whole) command
+	set fn show_$WHO
+	proc $fn { } $str
+    }
+}
+
+# The Debug Uart is special..
+set str ""
+
+
+# For every sub-register
+foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR 
+    DBGU_CSR DBGU_RHR DBGU_THR DBGU_BRGR DBGU_CIDR DBGU_EXID DBGU_FNTR} {
+
+    # Create a command for this specific register.
+    proc show_$REG { } "show_mmr32_reg $REG"
+    
+    # Add this command to the Device(as a whole) command
+    set str "$str\nshow_$REG"
+}
+
+# Now - create the DEVICE(as a whole) command
+proc show_DBGU { } $str
+
+unset str
+
+proc show_DBGU_MR_helper { NAME ADDR VAL } { show_mmr_USx_MR_helper $NAME $ADDR $VAL }
+
+
+