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| author | mlu <mlu@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-10-02 16:39:50 +0000 |
|---|---|---|
| committer | mlu <mlu@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-10-02 16:39:50 +0000 |
| commit | 1b90a9f5ebf19edc47d4e7325e38547616c9b4ee (patch) | |
| tree | 93d3867669ce48bce39515d3eb78e6341789e2d4 /src | |
| parent | 84dabdcc72d552c9078d00a22ea68e41e8d6765e (diff) | |
| download | openocd+libswd-1b90a9f5ebf19edc47d4e7325e38547616c9b4ee.tar.gz openocd+libswd-1b90a9f5ebf19edc47d4e7325e38547616c9b4ee.tar.bz2 openocd+libswd-1b90a9f5ebf19edc47d4e7325e38547616c9b4ee.tar.xz openocd+libswd-1b90a9f5ebf19edc47d4e7325e38547616c9b4ee.zip | |
More error reporting in Cortex_a8 execute_opcode
git-svn-id: svn://svn.berlios.de/openocd/trunk@2793 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/cortex_a8.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 7f8e2527..821d7194 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -165,8 +165,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) + { + LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode); return retval; } + } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode); @@ -176,8 +179,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) + { + LOG_ERROR("Could not read DSCR register"); return retval; } + } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ return retval; |