ARM: start generalized base type

Rename "struct armv4_5_common_s" as "struct arm".  It needs
a bit more work to be properly generic, and to move out of
this header, but it's the best start we have on that today.

Add and initialize an optional ETM pointer, since that will
be the first thing that gets generalized.

The intent being:  all ARMs should eventually derive from
this "struct arm", so they can reuse the current ETM logic.
(And later, more.)  Currently the ARM cores that *don't* so
derive are only ARMv7-M (and thus Cortex-M3) and ARM11.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

2 files changed, 34 insertions, 19 deletions

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index d76ce759..4d87c083 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -73,25 +73,51 @@ enum
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
-typedef struct armv4_5_common_s
+/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
+#define armv4_5_common_s arm
+
+/**
+ * Represents a generic ARM core, with standard application registers.
+ *
+ * There are sixteen application registers (including PC, SP, LR) and a PSR.
+ * Cortex-M series cores do not support as many core states or shadowed
+ * registers as traditional ARM cores, and only support Thumb2 instructions.
+ */
+typedef struct arm
 {
 	int common_magic;
 	reg_cache_t *core_cache;
+
 	int /* armv4_5_mode */ core_mode;
 	enum armv4_5_state core_state;
+
+	/** Flag reporting unavailability of the BKPT instruction. */
 	bool is_armv4;
+
+	/** Handle for the Embedded Trace Module, if one is present. */
+	struct etm *etm;
+
 	int (*full_context)(struct target_s *target);
-	int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
-	int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
+	int (*read_core_reg)(struct target_s *target,
+			int num, enum armv4_5_mode mode);
+	int (*write_core_reg)(struct target_s *target,
+			int num, enum armv4_5_mode mode, uint32_t value);
 	void *arch_info;
 } armv4_5_common_t;
 
-static inline struct armv4_5_common_s *
-target_to_armv4_5(struct target_s *target)
+#define target_to_armv4_5 target_to_arm
+
+/** Convert target handle to generic ARM target state handle. */
+static inline struct arm *target_to_arm(struct target_s *target)
 {
 	return target->arch_info;
 }
 
+static inline bool is_arm(struct arm *arm)
+{
+	return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
+}
+
 typedef struct armv4_5_algorithm_s
 {
 	int common_magic;
diff --git a/src/target/etm.c b/src/target/etm.c
index b5718098..795e0564 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -1354,7 +1354,7 @@ static int handle_etm_config_command(struct command_context_s *cmd_ctx,
 		char *cmd, char **args, int argc)
 {
 	target_t *target;
-	armv4_5_common_t *armv4_5;
+	struct arm *arm;
 	arm7_9_common_t *arm7_9;
 	etm_portmode_t portmode = 0x0;
 	struct etm *etm_ctx;
@@ -1370,7 +1370,7 @@ static int handle_etm_config_command(struct command_context_s *cmd_ctx,
 		return ERROR_FAIL;
 	}
 
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	if (arm7_9_get_arch_pointers(target, &arm, &arm7_9) != ERROR_OK)
 	{
 		command_print(cmd_ctx, "target '%s' is '%s'; not an ARM",
 				target->cmd_name, target_get_name(target));
@@ -1461,22 +1461,11 @@ static int handle_etm_config_command(struct command_context_s *cmd_ctx,
 	etm_ctx->target = target;
 	etm_ctx->trigger_percent = 50;
 	etm_ctx->trace_data = NULL;
-	etm_ctx->trace_depth = 0;
 	etm_ctx->portmode = portmode;
-	etm_ctx->tracemode = 0x0;
 	etm_ctx->core_state = ARMV4_5_STATE_ARM;
-	etm_ctx->image = NULL;
-	etm_ctx->pipe_index = 0;
-	etm_ctx->data_index = 0;
-	etm_ctx->current_pc = 0x0;
-	etm_ctx->pc_ok = 0;
-	etm_ctx->last_branch = 0x0;
-	etm_ctx->last_branch_reason = 0x0;
-	etm_ctx->last_ptr = 0x0;
-	etm_ctx->ptr_ok = 0x0;
-	etm_ctx->last_instruction = 0;
 
 	arm7_9->etm_ctx = etm_ctx;
+	arm->etm = etm_ctx;
 
 	return etm_register_user_commands(cmd_ctx);
 }