ARM: fix Thumb mode handling when single-stepping register based branch insns

Currently, OpenOCD is always caching the PC value without the T bit.
This means that assignment to the PC register must clear that bit and set
the processor state to Thumb when it is set.  And when the PC register
value is transferred to another register or stored into memory then
the T bit must be restored.

Discussion: It is arguable if OpenOCd should have preserved the original
PC value which would have greatly simplified this code.  The processor
state could then be obtained simply by getting at bit 0 of the PC.  This
however would require special handling elsewhere instead since the T bit
is not always relevant (like when PC is used with ALU insns or as an index
with some addressing modes).  It is unclear which way would be simpler in
the end.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

1 files changed, 33 insertions, 22 deletions

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 5af2c129..c50a52cd 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -380,7 +380,8 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 			else if (instruction.type == ARM_BL)
 			{
 				uint32_t old_pc = sim->get_reg(sim, 15);
-				sim->set_reg_mode(sim, 14, old_pc + 4);
+				int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+				sim->set_reg_mode(sim, 14, old_pc + 4 + T);
 				sim->set_reg(sim, 15, target);
 			}
 			else if (instruction.type == ARM_BX)
@@ -398,7 +399,8 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 			else if (instruction.type == ARM_BLX)
 			{
 				uint32_t old_pc = sim->get_reg(sim, 15);
-				sim->set_reg_mode(sim, 14, old_pc + 4);
+				int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+				sim->set_reg_mode(sim, 14, old_pc + 4 + T);
 
 				if (target & 0x1)
 				{
@@ -465,24 +467,24 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 		if (dry_run_pc)
 		{
 			if (instruction.info.data_proc.Rd == 15)
-			{
-				*dry_run_pc = Rd;
-				return ERROR_OK;
-			}
+				*dry_run_pc = Rd & ~1;
 			else
-			{
 				*dry_run_pc = current_pc + instruction_size;
-			}
 
 			return ERROR_OK;
 		}
 		else
 		{
+			if (instruction.info.data_proc.Rd == 15) {
+				sim->set_reg_mode(sim, 15, Rd & ~1);
+				if (Rd & 1)
+					sim->set_state(sim, ARMV4_5_STATE_THUMB);
+				else
+					sim->set_state(sim, ARMV4_5_STATE_ARM);
+				return ERROR_OK;
+			}
 			sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
 			LOG_WARNING("no updating of flags yet");
-
-			if (instruction.info.data_proc.Rd == 15)
-				return ERROR_OK;
 		}
 	}
 	/* compare instructions (CMP, CMN, TST, TEQ) */
@@ -566,15 +568,9 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 		if (dry_run_pc)
 		{
 			if (instruction.info.load_store.Rd == 15)
-			{
-				*dry_run_pc = load_value;
-				return ERROR_OK;
-			}
+				*dry_run_pc = load_value & ~1;
 			else
-			{
 				*dry_run_pc = current_pc + instruction_size;
-			}
-
 			return ERROR_OK;
 		}
 		else
@@ -584,10 +580,16 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 			{
 				sim->set_reg_mode(sim, instruction.info.load_store.Rn, modified_address);
 			}
-			sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
 
-			if (instruction.info.load_store.Rd == 15)
+			if (instruction.info.load_store.Rd == 15) {
+				sim->set_reg_mode(sim, 15, load_value & ~1);
+				if (load_value & 1)
+					sim->set_state(sim, ARMV4_5_STATE_THUMB);
+				else
+					sim->set_state(sim, ARMV4_5_STATE_ARM);
 				return ERROR_OK;
+			}
+			sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
 		}
 	}
 	/* load multiple instruction */
@@ -636,7 +638,7 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 		{
 			if (instruction.info.load_store_multiple.register_list & 0x8000)
 			{
-				*dry_run_pc = load_values[15];
+				*dry_run_pc = load_values[15] & ~1;
 				return ERROR_OK;
 			}
 		}
@@ -657,7 +659,16 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 			{
 				if (instruction.info.load_store_multiple.register_list & (1 << i))
 				{
-					sim->set_reg_mode(sim, i, load_values[i]);
+					if (i == 15) {
+						uint32_t val = load_values[i];
+					sim->set_reg_mode(sim, i, val & ~1);
+					if (val & 1)
+						sim->set_state(sim, ARMV4_5_STATE_THUMB);
+					else
+						sim->set_state(sim, ARMV4_5_STATE_ARM);
+					} else {
+						sim->set_reg_mode(sim, i, load_values[i]);
+					}
 				}
 			}