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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-01-14 14:10:36 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-01-14 14:10:36 +0000 |
| commit | 882a2712052d25fc15535e6199b4c663a5280c20 (patch) | |
| tree | 42f8cb8669f5b3c3dd896bcd40daa53529705fe4 /src | |
| parent | 9d19f3860f8fca6105e3e39bd95448867b10cd91 (diff) | |
| download | openocd+libswd-882a2712052d25fc15535e6199b4c663a5280c20.tar.gz openocd+libswd-882a2712052d25fc15535e6199b4c663a5280c20.tar.bz2 openocd+libswd-882a2712052d25fc15535e6199b4c663a5280c20.tar.xz openocd+libswd-882a2712052d25fc15535e6199b4c663a5280c20.zip | |
Alan Carvalho de Assis <acassis@gmail.com> small fix to move us in the right direction.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1316 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/target/imx31.cfg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/target/imx31.cfg b/src/target/target/imx31.cfg index acdc45a1..3d4883b7 100644 --- a/src/target/target/imx31.cfg +++ b/src/target/target/imx31.cfg @@ -45,14 +45,14 @@ jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJ # SDMA_BYPASS - disables SDMA - # # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e -irmask 0x1f -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID # No IDCODE for this TAP jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0 # Per section 40.17.1, table 40-85 the IR register is 4 bits # But this conflicts with Diagram 6-13, "3bits ir and drs" -jtag newtap $_CHIPNAME smda -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_SDMATAPID +jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_SDMATAPID set _TARGETNAME [format "%s.cpu" $_CHIPNAME] target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME |