- single core context used, removed debug context as thought unnecessary.

- DCRDR now used to access special core registers - info is currently omitted from the cortex_m3 TRM ARM have told me this is the preferred access method and the docs will be updated soon.
- now checks for User Thread Mode and Thread mode when halted.
- removed repeated function declarations from command.c
- cortex_m3_prepare_reset_halt removed, updated cortex_m3_assert_reset to suit

git-svn-id: svn://svn.berlios.de/openocd/trunk@558 b42882b7-edfa-0310-969c-e2dbd0fdcd60

7 files changed, 136 insertions, 273 deletions

diff --git a/src/flash/stellaris.c b/src/flash/stellaris.c
index 502659e3..309772e3 100644
--- a/src/flash/stellaris.c
+++ b/src/flash/stellaris.c
@@ -768,7 +768,6 @@ int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32
 	
 	armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 	armv7m_info.core_mode = ARMV7M_MODE_ANY;
-	armv7m_info.core_state = ARMV7M_STATE_THUMB;
 	
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
diff --git a/src/flash/stm32x.c b/src/flash/stm32x.c
index e981310a..e85c0e5a 100644
--- a/src/flash/stm32x.c
+++ b/src/flash/stm32x.c
@@ -459,7 +459,6 @@ int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 co
 	
 	armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 	armv7m_info.core_mode = ARMV7M_MODE_ANY;
-	armv7m_info.core_state = ARMV7M_STATE_THUMB;
 	
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
diff --git a/src/helper/binarybuffer.c b/src/helper/binarybuffer.c
index 03e2b7e3..6aa847aa 100644
--- a/src/helper/binarybuffer.c
+++ b/src/helper/binarybuffer.c
@@ -29,10 +29,6 @@
 
 #include "binarybuffer.h"
 
-int buf_set_u32(u8* buffer, unsigned int first, unsigned int num, u32 value);
-u32 buf_get_u32(u8* buffer, unsigned int first, unsigned int num);
-u32 flip_u32(u32 value, unsigned int num);
-
 const unsigned char bit_reverse_table256[] = 
 {
   0x00, 0x80, 0x40, 0xC0, 0x20, 0xA0, 0x60, 0xE0, 0x10, 0x90, 0x50, 0xD0, 0x30, 0xB0, 0x70, 0xF0, 
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index f79305f2..81b477a9 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -42,12 +42,7 @@
 
 char* armv7m_mode_strings[] =
 {
-	"Handler", "Thread"
-};
-
-char* armv7m_state_strings[] =
-{
-	"Thumb", "Debug"
+	"Thread", "Thread (User)", "Handler", 
 };
 
 char* armv7m_exception_strings[] =
@@ -62,22 +57,10 @@ char* armv7m_core_reg_list[] =
 	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
 	"sp", "lr", "pc",
 	"xPSR", "msp", "psp",
-	/* Registers accessed through MSR instructions */
-	/* "apsr", "iapsr", "ipsr", "epsr", */
+	/* Registers accessed through special reg 20 */
 	"primask", "basepri", "faultmask", "control"
 };
 
-char* armv7m_core_dbgreg_list[] =
-{
-	/* Registers accessed through core debug */
-	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
-	"sp", "lr", "pc",
-	"xPSR", "msp", "psp",
-	/* Registers accessed through MSR instructions */
-	/* "dbg_apsr", "iapsr", "ipsr", "epsr", */
-	"primask", "basepri", "faultmask", "dbg_control"
-};
-
 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 
 reg_t armv7m_gdb_dummy_fp_reg =
@@ -116,74 +99,15 @@ armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
 	{17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
 	{18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 
-	/*  CORE_SP are accesible using MSR and MRS instructions */
-#if 0
-	{0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
-	{0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
-	{0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
-	{0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
-#endif
-
-	{0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
-	{0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
-	{0x13, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
-	{0x14, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
+	/*  CORE_SP are accesible using coreregister 20 */
+	{19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
+	{20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
+	{21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
+	{22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
 };
 
 int armv7m_core_reg_arch_type = -1;
 
-/* Keep different contexts for the process being debugged and debug algorithms */
-enum armv7m_runcontext armv7m_get_context(target_t *target)
-{
-	/* get pointers to arch-specific information */
-	armv7m_common_t *armv7m = target->arch_info;
-	
-	if (armv7m->process_context == armv7m->core_cache)
-		return ARMV7M_PROCESS_CONTEXT;
-	if (armv7m->debug_context == armv7m->core_cache)
-		return ARMV7M_DEBUG_CONTEXT;
-	
-	LOG_ERROR("Invalid runcontext");
-	exit(-1);
-}
-
-int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
-{
-	int i;
-	/* get pointers to arch-specific information */
-	armv7m_common_t *armv7m = target->arch_info;
-	
-	if ((target->state != TARGET_HALTED) && (target->state != TARGET_RESET))
-	{
-		LOG_WARNING("target not halted, switch context ");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	if (new_ctx == armv7m_get_context(target))
-		return ERROR_OK;
-		
-	switch (new_ctx)
-	{
-		case ARMV7M_PROCESS_CONTEXT:
-			 armv7m->core_cache = armv7m->process_context;
-			 break;
-		case ARMV7M_DEBUG_CONTEXT:
-			 armv7m->core_cache = armv7m->debug_context;
-			 break;
-		default:
-			LOG_ERROR("Invalid runcontext");
-			exit(-1);		
-	} 
-	/* Mark registers in new context as dirty to force reload when run */
-	
-	for (i = 0; i < armv7m->core_cache->num_regs; i++)
-	{
-		armv7m->core_cache->reg_list[i].dirty = 1;
-	}
-	
-	return ERROR_OK;
-}
-
 int armv7m_restore_context(target_t *target)
 {
 	int i;
@@ -333,7 +257,7 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
 	
 	for (i = 0; i < 16; i++)
 	{
-		(*reg_list)[i] = &armv7m->process_context->reg_list[i];
+		(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 	}
 	
 	for (i = 16; i < 24; i++)
@@ -345,8 +269,8 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
 	
 	/* ARMV7M is always in thumb mode, try to make GDB understand this
 	 * if it does not support this arch */
-	armv7m->process_context->reg_list[15].value[0] |= 1;	
-	(*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];	
+	armv7m->core_cache->reg_list[15].value[0] |= 1;
+	(*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 	return ERROR_OK;
 }
 
@@ -355,10 +279,12 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
 	/* get pointers to arch-specific information */
 	armv7m_common_t *armv7m = target->arch_info;
 	armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
+	enum armv7m_mode core_mode = armv7m->core_mode;
 	int retval = ERROR_OK;
 	u32 pc;
 	int i;
-
+	u32 context[ARMV7NUMCOREREGS];
+	
 	if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 	{
 		LOG_ERROR("current target isn't an ARMV7M target");
@@ -373,7 +299,12 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
 	
 	/* refresh core register cache */
 	/* Not needed if core register cache is always consistent with target process state */ 
-	armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
+	for (i = 0; i < ARMV7NUMCOREREGS; i++)
+	{
+		if (!armv7m->core_cache->reg_list[i].valid)
+			armv7m->read_core_reg(target, i);
+		context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
+	}
 	
 	for (i = 0; i < num_mem_params; i++)
 	{
@@ -401,6 +332,14 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
 		armv7m_set_core_reg(reg, reg_params[i].value);
 	}
 	
+	if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
+	{
+		LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
+		buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
+		armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
+		armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
+	}
+	
 	/* ARMV7M always runs in Thumb state */
 	if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
 	{
@@ -452,7 +391,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
 	{
 		if (reg_params[i].direction != PARAM_OUT)
 		{
-			reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
+			reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 		
 			if (!reg)
 			{
@@ -470,6 +409,16 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
 		}
 	}
 	
+	for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
+	{
+		LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
+		buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
+		armv7m->core_cache->reg_list[i].valid = 1;
+		armv7m->core_cache->reg_list[i].dirty = 1;
+	}
+	
+	armv7m->core_mode = core_mode;
+	
 	return retval;
 }
 
@@ -478,13 +427,12 @@ int armv7m_arch_state(struct target_s *target)
 	/* get pointers to arch-specific information */
 	armv7m_common_t *armv7m = target->arch_info;
 	
-	LOG_USER("target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
-		 armv7m_state_strings[armv7m->core_state],
-		 target_debug_reason_strings[target->debug_reason],
-		 armv7m_mode_strings[armv7m->core_mode],
-		 armv7m_exception_string(armv7m->exception_number),
-		 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
-		 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
+	LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
+		target_debug_reason_strings[target->debug_reason],
+		armv7m_mode_strings[armv7m->core_mode],
+		armv7m_exception_string(armv7m->exception_number),
+		buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
+		buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
 	
 	return ERROR_OK;
 }
@@ -511,7 +459,6 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target)
 	cache->num_regs = num_regs;
 	(*cache_p) = cache;
 	armv7m->core_cache = cache;
-	armv7m->process_context = cache;
 	
 	for (i = 0; i < num_regs; i++)
 	{
@@ -528,30 +475,6 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target)
 		reg_list[i].arch_type = armv7m_core_reg_arch_type;
 		reg_list[i].arch_info = &arch_info[i];
 	}
-
-	/* Build the debug context cache*/
-	cache = malloc(sizeof(reg_cache_t));
-	reg_list = malloc(sizeof(reg_t) * num_regs);
-
-	cache->name = "arm v7m debug registers";
-	cache->next = NULL;
-	cache->reg_list = reg_list;
-	cache->num_regs = num_regs;
-	armv7m->debug_context = cache;
-	armv7m->process_context->next = cache;
-
-	for (i = 0; i < num_regs; i++)
-	{
-		reg_list[i].name = armv7m_core_dbgreg_list[i];
-		reg_list[i].size = 32;
-		reg_list[i].value = calloc(1, 4);
-		reg_list[i].dirty = 0;
-		reg_list[i].valid = 0;
-		reg_list[i].bitfield_desc = NULL;
-		reg_list[i].num_bitfields = 0;
-		reg_list[i].arch_type = armv7m_core_reg_arch_type;
-		reg_list[i].arch_info = &arch_info[i];
-	}
 	
 	return cache;
 }
@@ -568,7 +491,6 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
 	/* register arch-specific functions */
 	
 	target->arch_info = armv7m;
-	armv7m->core_state = ARMV7M_STATE_THUMB;
 	armv7m->read_core_reg = armv7m_read_core_reg;
 	armv7m->write_core_reg = armv7m_write_core_reg;
 	
@@ -631,7 +553,6 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
 	
 	armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 	armv7m_info.core_mode = ARMV7M_MODE_ANY;
-	armv7m_info.core_state = ARMV7M_STATE_THUMB;
 	
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
@@ -659,3 +580,4 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
 	return ERROR_OK;
 }
 
+
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index a29593da..8199c23a 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -29,19 +29,14 @@
 
 enum armv7m_mode
 {
-	ARMV7M_MODE_HANDLER = 0, 
-	ARMV7M_MODE_THREAD = 1, 
+	ARMV7M_MODE_THREAD = 0,
+	ARMV7M_MODE_USER_THREAD = 1,
+	ARMV7M_MODE_HANDLER = 2,
 	ARMV7M_MODE_ANY = -1
 };
 
 extern char* armv7m_mode_strings[];
 
-enum armv7m_state
-{
-	ARMV7M_STATE_THUMB,
-	ARMV7M_STATE_DEBUG,
-};
-
 enum armv7m_regtype
 {
 	ARMV7M_REGISTER_CORE_GP,
@@ -49,13 +44,6 @@ enum armv7m_regtype
 	ARMV7M_REGISTER_MEMMAP
 };
 
-enum armv7m_runcontext
-{
-	ARMV7M_PROCESS_CONTEXT,
-	ARMV7M_DEBUG_CONTEXT
-};
-
-extern char* armv7m_state_strings[];
 extern char* armv7m_exception_strings[];
 
 extern char *armv7m_exception_string(int number);
@@ -80,11 +68,8 @@ typedef struct armv7m_common_s
 {
 	int common_magic;
 	reg_cache_t *core_cache;
-	reg_cache_t *process_context;
-	reg_cache_t *debug_context;
 	enum armv7m_mode core_mode;
-	enum armv7m_state core_state;
-	int  exception_number;
+	int exception_number;
 	
 	/* Direct processor core register read and writes */
 	int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
@@ -108,9 +93,8 @@ typedef struct armv7m_common_s
 typedef struct armv7m_algorithm_s
 {
 	int common_magic;
-		
+	
 	enum armv7m_mode core_mode;
-	enum armv7m_state core_state;
 } armv7m_algorithm_t;
 
 typedef struct armv7m_core_reg_s
@@ -137,9 +121,6 @@ extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem
 
 extern int armv7m_invalidate_core_regs(target_t *target);
 
-extern enum armv7m_runcontext armv7m_get_context(target_t *target);
-extern int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx);
-extern enum armv7m_runcontext armv7m_get_context(target_t *target);
 extern int armv7m_restore_context(target_t *target);
 
 extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 19b0a758..653ebab0 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -43,10 +43,8 @@
 int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
 
 /* forward declarations */
-void cortex_m3_unset_all_breakpoints_and_watchpoints(struct target_s *target);
 void cortex_m3_enable_breakpoints(struct target_s *target);
 void cortex_m3_enable_watchpoints(struct target_s *target);
-void cortex_m3_disable_bkpts_and_wpts(struct target_s *target);
 int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
 int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int cortex_m3_quit();
@@ -201,8 +199,6 @@ int cortex_m3_endreset_event(target_t *target)
 	}
 	swjdp_transaction_endcheck(swjdp);
 	
-	/* We are in process context */
-	armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
 	armv7m_invalidate_core_regs(target);
 	return ERROR_OK;
 }
@@ -323,16 +319,25 @@ int cortex_m3_debug_entry(target_t *target)
 		cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 	}
 
-	/* Now we can load SP core registers */	
+	/* Now we can load SP core registers */
 	for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++)
 	{
 		if (!armv7m->core_cache->reg_list[i].valid)
-			armv7m->read_core_reg(target, i);		
+			armv7m->read_core_reg(target, i);
 	}
 
 	/* Are we in an exception handler */
-    armv7m->core_mode = (xPSR & 0x1FF) ? ARMV7M_MODE_HANDLER : ARMV7M_MODE_THREAD;
-    armv7m->exception_number = xPSR & 0x1FF;
+	if (xPSR & 0x1FF)
+	{
+		armv7m->core_mode = ARMV7M_MODE_HANDLER;
+		armv7m->exception_number = (xPSR & 0x1FF);
+	}
+	else
+	{
+		armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
+		armv7m->exception_number = 0;
+	}
+	
 	if (armv7m->exception_number)
 	{
 		cortex_m3_examine_exception_reason(target);
@@ -412,9 +417,12 @@ int cortex_m3_poll(target_t *target)
 		target->state = TARGET_SLEEP;
 	*/
 
+#if 0
     /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script  */
-    ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
-	LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]);	
+	ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+	LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]);
+#endif
+	
 	return ERROR_OK;
 }
 
@@ -472,13 +480,6 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
 	swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 	u32 dcb_dhcsr = 0;
 	int retval, timeout = 0;
-	
-	/* Check that we are using process_context, or change and print warning */
-	if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT)
-	{
-		LOG_DEBUG("Changing to process contex registers");
-		armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
-	}
 
 	/* Enter debug state on reset, cf. end_reset_event() */
 	ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET );
@@ -512,28 +513,6 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
 	return ERROR_OK;
 }
 
-int cortex_m3_prepare_reset_halt(struct target_s *target)
-{
-	armv7m_common_t *armv7m = target->arch_info;
-	cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-	swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
-	u32 dcb_demcr, dcb_dhcsr;
-	
-	/* Enable debug requests */
-	ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
-	if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
-		ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN );
-	
-	/* Enter debug state on reset, cf. end_reset_event() */
-	ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET );
-	
-	ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
-	ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
-	LOG_DEBUG("dcb_dhcsr 0x%x, dcb_demcr 0x%x, ", dcb_dhcsr, dcb_demcr);
-	
-	return ERROR_OK;
-}
-
 int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
 {
 	/* get pointers to arch-specific information */
@@ -551,13 +530,6 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
 	
 	if (!debug_execution)
 	{
-		/* Check that we are using process_context, or change and print warning */
-		if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT)
-		{
-			LOG_DEBUG("Incorrect context in resume");
-			armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
-		}
-		
 		target_free_all_working_areas(target);
 		cortex_m3_enable_breakpoints(target);
 		cortex_m3_enable_watchpoints(target);
@@ -568,12 +540,6 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
 	dcb_dhcsr = DBGKEY | C_DEBUGEN;
 	if (debug_execution)
 	{
-		/* Check that we are using debug_context, or change and print warning */
-		if (armv7m_get_context(target) != ARMV7M_DEBUG_CONTEXT)
-		{
-			LOG_DEBUG("Incorrect context in debug_exec resume");
-			armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
-		}
 		/* Disable interrupts */
 		/* 
 		   We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
@@ -604,10 +570,10 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
 		/* Single step past breakpoint at current address */
 		if ((breakpoint = breakpoint_find(target, resume_pc)))
 		{
-				LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
-				cortex_m3_unset_breakpoint(target, breakpoint);
-				cortex_m3_single_step_core(target);
-				cortex_m3_set_breakpoint(target, breakpoint);
+			LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
+			cortex_m3_unset_breakpoint(target, breakpoint);
+			cortex_m3_single_step_core(target);
+			cortex_m3_set_breakpoint(target, breakpoint);
 		}
 	}
 
@@ -651,13 +617,6 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
-	/* Check that we are using process_context, or change and print warning */
-	if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT)
-	{
-		LOG_WARNING("Incorrect context in step, must be process");
-		armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
-	}
 
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	if (!current)
@@ -679,9 +638,8 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle
 	ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY| C_STEP | C_DEBUGEN);
 	ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 
-	/* If we run in process context then registers are now invalid */
-	if (armv7m_get_context(target) == ARMV7M_PROCESS_CONTEXT)
-		armv7m_invalidate_core_regs(target);
+	/* registers are now invalid */
+	armv7m_invalidate_core_regs(target);
 	
 	if (breakpoint)
 		cortex_m3_set_breakpoint(target, breakpoint);
@@ -700,7 +658,6 @@ int cortex_m3_assert_reset(target_t *target)
 	armv7m_common_t *armv7m = target->arch_info;
 	cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 	swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
-	int retval;
 	
 	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 	
@@ -709,10 +666,12 @@ int cortex_m3_assert_reset(target_t *target)
 		LOG_ERROR("Can't assert SRST");
 		return ERROR_FAIL;
 	}
-	/* FIX!!! should this be removed as we're asserting trst anyway? */
-	if ((retval=cortex_m3_prepare_reset_halt(target))!=ERROR_OK)
-		return retval;
 	
+	/* Enable debug requests */
+	ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
+		ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN );
+		
 	ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
 	
 	if (target->reset_mode == RESET_RUN)
@@ -724,22 +683,27 @@ int cortex_m3_assert_reset(target_t *target)
 		cortex_m3_clear_halt(target);
 							
 		/* Enter debug state on reset, cf. end_reset_event() */	
-		ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN );
 		ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
 	}
+	else
+	{
+		/* Enter debug state on reset, cf. end_reset_event() */
+		ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET );
+	}
 	
 	if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
 	{
-	/* assert SRST and TRST */
-	/* system would get ouf sync if we didn't reset test-logic, too */
-	jtag_add_reset(1, 1);
-	jtag_add_sleep(5000);
+		/* assert SRST and TRST */
+		/* system would get ouf sync if we didn't reset test-logic, too */
+		jtag_add_reset(1, 1);
+		jtag_add_sleep(5000);
 	}
 
 	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 	{
 		jtag_add_reset(1, 1);
-	} else
+	}
+	else
 	{
 		jtag_add_reset(0, 1);
 	}
@@ -747,13 +711,6 @@ int cortex_m3_assert_reset(target_t *target)
 	target->state = TARGET_RESET;
 	jtag_add_sleep(50000);
 	
-	#if 0
-	if ((target->reset_mode==RESET_HALT)||(target->reset_mode==RESET_INIT))
-	{
-		cortex_m3_halt(target);
-	}
-	#endif
-	armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
 	armv7m_invalidate_core_regs(target);
 
 	return ERROR_OK;
@@ -769,11 +726,6 @@ int cortex_m3_deassert_reset(target_t *target)
 	return ERROR_OK;
 }
 
-void cortex_m3_unset_all_breakpoints_and_watchpoints(struct target_s *target)
-{
-
-}
-
 void cortex_m3_enable_breakpoints(struct target_s *target)
 {
 	breakpoint_t *breakpoint = target->breakpoints;
@@ -1118,22 +1070,28 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
 	else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
 	{
 		/* read other registers */
-		u32 savedram;
-		u32 SYSm;
-		u32 instr;
-		SYSm = num & 0x1F;
+		ahbap_read_coreregister_u32(swjdp, value, 20);
 		
-		ahbap_read_system_u32(swjdp, 0x20000000, &savedram);
-		instr = ARMV7M_T_MRS(0, SYSm);
-		ahbap_write_system_u32(swjdp, 0x20000000, ARMV7M_T_MRS(0, SYSm));
-		ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
-		cortex_m3_single_step_core(target);
-		ahbap_read_coreregister_u32(swjdp, value, 0);
-		armv7m->core_cache->reg_list[0].dirty = armv7m->core_cache->reg_list[0].valid;
-		armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
-		ahbap_write_system_u32(swjdp, 0x20000000, savedram);
-		swjdp_transaction_endcheck(swjdp);
-		LOG_DEBUG("load from special reg %i value 0x%x", SYSm, *value);
+		switch (num)
+		{
+			case 19:
+				*value = buf_get_u32((u8*)value, 0, 8);
+				break;
+				
+			case 20:
+				*value = buf_get_u32((u8*)value, 8, 8);
+				break;
+				
+			case 21:
+				*value = buf_get_u32((u8*)value, 16, 8);
+				break;
+				
+			case 22:
+				*value = buf_get_u32((u8*)value, 24, 8);
+				break;
+		}
+		
+		LOG_DEBUG("load from special reg %i value 0x%x", num, *value);
 	}
 	else
 	{
@@ -1146,6 +1104,7 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
 int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value)
 {
 	int retval;
+	u32 reg;
 	
 	/* get pointers to arch-specific information */
 	armv7m_common_t *armv7m = target->arch_info;
@@ -1166,23 +1125,31 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
 	else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
 	{
 		/* write other registers */
-		u32 savedram , tempr0;
-		u32 SYSm;
-		u32 instr;
-		SYSm = num & 0x1F;
 		
-		ahbap_read_system_u32(swjdp, 0x20000000, &savedram);
-		instr = ARMV7M_T_MSR(SYSm, 0);
-		ahbap_write_system_u32(swjdp, 0x20000000, ARMV7M_T_MSR(SYSm, 0));
-		ahbap_read_coreregister_u32(swjdp, &tempr0, 0);
-		ahbap_write_coreregister_u32(swjdp, value, 0);
-		ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
-		cortex_m3_single_step_core(target);
-		ahbap_write_coreregister_u32(swjdp, tempr0, 0);
-		armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
-		ahbap_write_system_u32(swjdp, 0x20000000, savedram);
-		swjdp_transaction_endcheck(swjdp);
-		LOG_DEBUG("write special reg %i value 0x%x ", SYSm, value);
+		ahbap_read_coreregister_u32(swjdp, &reg, 20);
+		
+		switch (num)
+		{
+			case 19:
+				buf_set_u32((u8*)&reg, 0, 8, value);
+				break;
+				
+			case 20:
+				buf_set_u32((u8*)&reg, 8, 8, value);
+				break;
+				
+			case 21:
+				buf_set_u32((u8*)&reg, 16, 8, value);
+				break;
+				
+			case 22:
+				buf_set_u32((u8*)&reg, 24, 8, value);
+				break;
+		}
+		
+		ahbap_write_coreregister_u32(swjdp, reg, 20);
+		
+		LOG_DEBUG("write special reg %i value 0x%x ", num, value);
 	}
 	else
 	{
diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index 17c2b47b..0072e84b 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -173,7 +173,6 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle
 int cortex_m3_assert_reset(target_t *target);
 int cortex_m3_deassert_reset(target_t *target);
 int cortex_m3_soft_reset_halt(struct target_s *target);
-int cortex_m3_prepare_reset_halt(struct target_s *target);
 
 int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);