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author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-19 13:09:19 -0800 |
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committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-19 13:09:19 -0800 |
commit | abe8b43755fdbc4fe92b966c48b367159deff226 (patch) | |
tree | 45ab3a2c03476db594f54c966d043fcb07b5fc28 /src | |
parent | 64934d9204dc854d40893634a66e29ece09ad578 (diff) | |
download | openocd+libswd-abe8b43755fdbc4fe92b966c48b367159deff226.tar.gz openocd+libswd-abe8b43755fdbc4fe92b966c48b367159deff226.tar.bz2 openocd+libswd-abe8b43755fdbc4fe92b966c48b367159deff226.tar.xz openocd+libswd-abe8b43755fdbc4fe92b966c48b367159deff226.zip |
ETM: add "etm trigger_debug" command
In conjunction with manual register setup, this lets the ETM trigger
cause entry to debug state. It should make it easier to test and
bugfix the ETM code, by enabling non-trace usage and isolating bugs
specific to thef ETM support. (One current issue being that trace
data collection using the ETB doesn't yet behave.)
For example, many ARM9 cores with an ETM should be able to implement
four more (simple) breakpoints and two more (simple) watchpoints than
the EmbeddedICE supports. Or, they should be able to support complex
breakpoints, incorporating ETM sequencer, counters, and/or subroutine
entry/exit criteria int criteria used to trigger debug entry.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r-- | src/target/etm.c | 66 |
1 files changed, 62 insertions, 4 deletions
diff --git a/src/target/etm.c b/src/target/etm.c index a506d1c4..d22bc407 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -446,12 +446,15 @@ int etm_setup(struct target *target) etm_ctrl_value = (etm_ctrl_value & ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK + & ~ETM_CTRL_DBGRQ & ~ETM_PORT_CLOCK_MASK) | etm_ctx->control; buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value); etm_store_reg(etm_ctrl_reg); + etm_ctx->control = etm_ctrl_value; + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; @@ -1338,8 +1341,6 @@ COMMAND_HANDLER(handle_etm_tracemode_command) if (!etm_ctrl_reg) return ERROR_FAIL; - etm_get_reg(etm_ctrl_reg); - etm->control &= ~TRACEMODE_MASK; etm->control |= tracemode & TRACEMODE_MASK; @@ -2016,6 +2017,56 @@ COMMAND_HANDLER(handle_etm_stop_command) return ERROR_OK; } +COMMAND_HANDLER(handle_etm_trigger_debug_command) +{ + struct target *target; + struct arm *arm; + struct etm_context *etm; + + target = get_current_target(CMD_CTX); + arm = target_to_arm(target); + if (!is_arm(arm)) + { + command_print(CMD_CTX, "ETM: %s isn't an ARM", + target_name(target)); + return ERROR_FAIL; + } + + etm = arm->etm; + if (!etm) + { + command_print(CMD_CTX, "ETM: no ETM configured for %s", + target_name(target)); + return ERROR_FAIL; + } + + if (CMD_ARGC == 1) { + struct reg *etm_ctrl_reg; + bool dbgrq; + + etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL); + if (!etm_ctrl_reg) + return ERROR_FAIL; + + COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq); + if (dbgrq) + etm->control |= ETM_CTRL_DBGRQ; + else + etm->control &= ~ETM_CTRL_DBGRQ; + + /* etm->control will be written to hardware + * the next time an "etm start" is issued. + */ + buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control); + } + + command_print(CMD_CTX, "ETM: %s debug halt", + (etm->control & ETM_CTRL_DBGRQ) + ? "triggers" + : "does not trigger"); + return ERROR_OK; +} + COMMAND_HANDLER(handle_etm_analyze_command) { struct target *target; @@ -2112,10 +2163,17 @@ static const struct command_registration etm_exec_command_handlers[] = { .help = "stop ETM trace collection", }, { + .name = "trigger_debug", + .handler = handle_etm_trigger_debug_command, + .mode = COMMAND_EXEC, + .help = "enable/disable debug entry on trigger", + .usage = "(enable | disable)", + }, + { .name = "analyze", - .handler = &handle_etm_analyze_command, + .handler = handle_etm_analyze_command, .mode = COMMAND_EXEC, - .help = "anaylze collected ETM trace", + .help = "analyze collected ETM trace", }, { .name = "image", |