allow minidrivers to implement inner loop of dcc memory writes

git-svn-id: svn://svn.berlios.de/openocd/trunk@879 b42882b7-edfa-0310-969c-e2dbd0fdcd60

3 files changed, 406 insertions, 407 deletions

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index cf5f2b36..0531cad6 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -64,13 +64,13 @@ int arm7_9_reinit_embeddedice(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	breakpoint_t *breakpoint = target->breakpoints;
-	
+
 	arm7_9->wp_available = 2;
 	arm7_9->wp0_used = 0;
 	arm7_9->wp1_used = 0;
-		
+
 	/* mark all hardware breakpoints as unset */
 	while (breakpoint)
 	{
@@ -80,13 +80,13 @@ int arm7_9_reinit_embeddedice(target_t *target)
 		}
 		breakpoint = breakpoint->next;
 	}
-		
+
 	if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
 	{
 		arm7_9->sw_bkpts_enabled = 0;
 		arm7_9_enable_sw_bkpts(target);
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -104,20 +104,20 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 	{
 		return -1;
 	}
-	
+
 	if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 	{
 		return -1;
 	}
-	
+
 	*armv4_5_p = armv4_5;
 	*arm7_9_p = arm7_9;
-	
+
 	return ERROR_OK;
 }
 
@@ -125,13 +125,13 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	if (arm7_9->force_hw_bkpts)
 		breakpoint->type = BKPT_HARD;
 
@@ -184,7 +184,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 			/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 			target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
-			
+
 			target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
 			if (verify != arm7_9->arm_bkpt)
 			{
@@ -199,7 +199,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 			/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
 			target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
-			
+
 			target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
 			if (verify != arm7_9->thumb_bkpt)
 			{
@@ -218,7 +218,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
@@ -230,7 +230,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		LOG_WARNING("breakpoint not set");
 		return ERROR_OK;
 	}
-	
+
 	if (breakpoint->type == BKPT_HARD)
 	{
 		if (breakpoint->set == 1)
@@ -276,40 +276,40 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	if (arm7_9->force_hw_bkpts)
 	{
 		LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
 		breakpoint->type = BKPT_HARD;
 	}
-	
+
 	if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
 	{
 		LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
-	
+
 	if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
 	{
 		LOG_INFO("no watchpoint unit available for hardware breakpoint");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
-	
+
 	if ((breakpoint->length != 2) && (breakpoint->length != 4))
 	{
 		LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
-	
+
 	if (breakpoint->type == BKPT_HARD)
 		arm7_9->wp_available--;
-	
+
 	return ERROR_OK;
 }
 
@@ -317,21 +317,21 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	if (breakpoint->set)
 	{
 		arm7_9_unset_breakpoint(target, breakpoint);
 	}
-	
+
 	if (breakpoint->type == BKPT_HARD)
 		arm7_9->wp_available++;
-	
+
 	return ERROR_OK;
 }
 
@@ -341,20 +341,20 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	int rw_mask = 1;
 	u32 mask;
-	
+
 	mask = watchpoint->length - 1;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	if (watchpoint->rw == WPT_ACCESS)
 		rw_mask = 0;
 	else
 		rw_mask = 1;
-	
+
 	if (!arm7_9->wp0_used)
 	{
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
@@ -382,13 +382,13 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 		jtag_execute_queue();
 		watchpoint->set = 2;
 		arm7_9->wp1_used = 2;
-	} 
+	}
 	else
 	{
 		LOG_ERROR("BUG: no hardware comparator available");
 		return ERROR_OK;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -396,19 +396,19 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	if (!watchpoint->set)
 	{
 		LOG_WARNING("breakpoint not set");
 		return ERROR_OK;
 	}
-	
+
 	if (watchpoint->set == 1)
 	{
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
@@ -430,25 +430,25 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	if (arm7_9->wp_available < 1)
 	{
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
-	
+
 	if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
 	{
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
-	
+
 	arm7_9->wp_available--;
-		
+
 	return ERROR_OK;
 }
 
@@ -456,20 +456,20 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	if (watchpoint->set)
 	{
 		arm7_9_unset_watchpoint(target, watchpoint);
 	}
-		
+
 	arm7_9->wp_available++;
-	
+
 	return ERROR_OK;
 }
 
@@ -478,17 +478,17 @@ int arm7_9_enable_sw_bkpts(struct target_s *target)
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	int retval;
-	
+
 	if (arm7_9->sw_bkpts_enabled)
 		return ERROR_OK;
-	
+
 	if (arm7_9->wp_available < 1)
 	{
 		LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 	arm7_9->wp_available--;
-	
+
 	if (!arm7_9->wp0_used)
 	{
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
@@ -514,13 +514,13 @@ int arm7_9_enable_sw_bkpts(struct target_s *target)
 		LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
 		return ERROR_FAIL;
 	}
-	
+
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
 		return ERROR_FAIL;
 	};
-	
+
 	return ERROR_OK;
 }
 
@@ -528,10 +528,10 @@ int arm7_9_disable_sw_bkpts(struct target_s *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (!arm7_9->sw_bkpts_enabled)
 		return ERROR_OK;
-	
+
 	if (arm7_9->sw_bkpts_enabled == 1)
 	{
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
@@ -554,12 +554,12 @@ int arm7_9_execute_sys_speed(struct target_s *target)
 {
 	int timeout;
 	int retval;
-	
+
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
-				
+
 	/* set RESTART instruction */
 	jtag_add_end_state(TAP_RTI);
 	if (arm7_9->need_bypass_before_restart) {
@@ -567,7 +567,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
 		arm_jtag_set_instr(jtag_info, 0xf, NULL);
 	}
 	arm_jtag_set_instr(jtag_info, 0x4, NULL);
-	
+
 	for (timeout=0; timeout<50; timeout++)
 	{
 		/* read debug status register */
@@ -577,14 +577,14 @@ int arm7_9_execute_sys_speed(struct target_s *target)
 		if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 				   && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 			break;
-		usleep(100000);	
+		usleep(100000);
 	}
 	if (timeout == 50)
 	{
 		LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 		return ERROR_TARGET_TIMEOUT;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -592,12 +592,12 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
 {
 	static int set=0;
 	static u8 check_value[4], check_mask[4];
-	
+
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
-				
+
 	/* set RESTART instruction */
 	jtag_add_end_state(TAP_RTI);
 	if (arm7_9->need_bypass_before_restart) {
@@ -605,11 +605,11 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
 		arm_jtag_set_instr(jtag_info, 0xf, NULL);
 	}
 	arm_jtag_set_instr(jtag_info, 0x4, NULL);
-	
+
 	if (!set)
 	{
 		/* check for DBGACK and SYSCOMP set (others don't care) */
-		
+
 		/* NB! These are constants that must be available until after next jtag_execute() and
 		   we evaluate the values upon first execution in lieu of setting up these constants
 		   during early setup.
@@ -618,7 +618,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
 		buf_set_u32(check_mask, 0, 32, 0x9);
 		set=1;
 	}
-	
+
 	/* read debug status register */
 	embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
 
@@ -632,18 +632,18 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	u32 *data;
 	int i;
-	
+
 	data = malloc(size * (sizeof(u32)));
-	
+
 	embeddedice_receive(jtag_info, data, size);
-	
+
 	for (i = 0; i < size; i++)
 	{
 		h_u32_to_le(buffer + (i * 4), data[i]);
 	}
-	
+
 	free(data);
-	
+
 	return ERROR_OK;
 }
 
@@ -654,29 +654,29 @@ int arm7_9_handle_target_request(void *priv)
 		return ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info; 
+	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
-	
-	
+
+
 	if (!target->dbg_msg_enabled)
 		return ERROR_OK;
-		
+
 	if (target->state == TARGET_RUNNING)
 	{
 		/* read DCC control register */
 		embeddedice_read_reg(dcc_control);
 		jtag_execute_queue();
-		
+
 		/* check W bit */
 		if (buf_get_u32(dcc_control->value, 1, 1) == 1)
 		{
 			u32 request;
-			
+
 			embeddedice_receive(jtag_info, &request, 1);
 			target_request(target, request);
 		}
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -693,7 +693,7 @@ int arm7_9_poll(target_t *target)
 	{
 		return retval;
 	}
-	
+
 	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 	{
 /*		LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
@@ -715,12 +715,12 @@ int arm7_9_poll(target_t *target)
 					}
 				}
 			}
-			
+
 			target->state = TARGET_HALTED;
-			
+
 			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 				return retval;
-			
+
 			if (check_pc)
 			{
 				reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
@@ -730,7 +730,7 @@ int arm7_9_poll(target_t *target)
 					LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
 				}
 			}
-			
+
 			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 		}
 		if (target->state == TARGET_DEBUG_RUNNING)
@@ -738,7 +738,7 @@ int arm7_9_poll(target_t *target)
 			target->state = TARGET_HALTED;
 			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 				return retval;
-			
+
 			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 		}
 		if (target->state != TARGET_HALTED)
@@ -751,7 +751,7 @@ int arm7_9_poll(target_t *target)
 		if (target->state != TARGET_DEBUG_RUNNING)
 			target->state = TARGET_RUNNING;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -768,7 +768,7 @@ int arm7_9_assert_reset(target_t *target)
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
-	
+
 	if (!(jtag_reset_config & RESET_HAS_SRST))
 	{
 		LOG_ERROR("Can't assert SRST");
@@ -780,9 +780,9 @@ int arm7_9_assert_reset(target_t *target)
 		/*
 		 * Some targets do not support communication while SRST is asserted. We need to
 		 * set up the reset vector catch here.
-		 * 
+		 *
 		 * If TRST is asserted, then these settings will be reset anyway, so setting them
-		 * here is harmless.  
+		 * here is harmless.
 		 */
 		if (arm7_9->has_vector_catch)
 		{
@@ -808,7 +808,7 @@ int arm7_9_assert_reset(target_t *target)
 	{
 		jtag_add_reset(0, 1);
 	}
-	
+
 
 	target->state = TARGET_RESET;
 	jtag_add_sleep(50000);
@@ -822,10 +822,10 @@ int arm7_9_assert_reset(target_t *target)
 int arm7_9_deassert_reset(target_t *target)
 {
 	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
-	
+
 	/* deassert reset lines */
 	jtag_add_reset(0, 0);
-	
+
 	return ERROR_OK;
 }
 
@@ -834,13 +834,13 @@ int arm7_9_clear_halt(target_t *target)
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
-	
+
 	/* we used DBGRQ only if we didn't come out of reset */
 	if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
 	{
 		/* program EmbeddedICE Debug Control Register to deassert DBGRQ
 		 */
-		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);	
+		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 		embeddedice_store_reg(dbg_ctrl);
 	}
 	else
@@ -867,13 +867,13 @@ int arm7_9_clear_halt(target_t *target)
 				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
 				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
 			}
-			/* control value always has to be restored, as it was either disabled, 
+			/* control value always has to be restored, as it was either disabled,
 			 * or enabled with possibly different bits
 			 */
 			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 		}
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -885,10 +885,10 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 	int i;
 	int retval;
-	
+
 	if ((retval=target_halt(target))!=ERROR_OK)
 		return retval;
-	
+
 	for (i=0; i<10; i++)
 	{
 		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
@@ -898,7 +898,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 			return retval;
 		/* do not eat all CPU, time out after 1 se*/
 		usleep(100*1000);
-		
+
 	}
 	if (i==10)
 	{
@@ -906,7 +906,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 		return ERROR_TARGET_TIMEOUT;
 	}
 	target->state = TARGET_HALTED;
-	
+
 	/* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 	 * ensure that DBGRQ is cleared
 	 */
@@ -914,9 +914,9 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 	embeddedice_store_reg(dbg_ctrl);
-	
+
 	arm7_9_clear_halt(target);
-	
+
 	/* if the target is in Thumb state, change to ARM state */
 	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
 	{
@@ -926,36 +926,36 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 		armv4_5->core_state = ARMV4_5_STATE_THUMB;
 		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
 	}
-	
+
 	/* all register content is now invalid */
 	armv4_5_invalidate_core_regs(target);
-	
+
 	/* SVC, ARM state, IRQ and FIQ disabled */
 	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
-	
+
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 	armv4_5->core_cache->reg_list[15].dirty = 1;
 	armv4_5->core_cache->reg_list[15].valid = 1;
-	
+
 	armv4_5->core_mode = ARMV4_5_MODE_SVC;
 	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
-	
+
 	/* reset registers */
 	for (i = 0; i <= 14; i++)
-	{	
+	{
 		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 	}
-	
+
 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
-	
+
 	return ERROR_OK;
 }
 
@@ -964,21 +964,21 @@ int arm7_9_halt(target_t *target)
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
-	
+
 	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
-	
+
 	if (target->state == TARGET_HALTED)
 	{
 		LOG_DEBUG("target was already halted");
 		return ERROR_OK;
 	}
-	
+
 	if (target->state == TARGET_UNKNOWN)
 	{
 		LOG_WARNING("target was in unknown state when halt was requested");
 	}
-	
-	if (target->state == TARGET_RESET) 
+
+	if (target->state == TARGET_RESET)
 	{
 		if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
 		{
@@ -991,8 +991,8 @@ int arm7_9_halt(target_t *target)
 			 * debug entry was already prepared in arm7_9_assert_reset()
 			 */
 			target->debug_reason = DBG_REASON_DBGRQ;
-			
-			return ERROR_OK; 
+
+			return ERROR_OK;
 		}
 	}
 
@@ -1003,7 +1003,7 @@ int arm7_9_halt(target_t *target)
 		if (arm7_9->set_special_dbgrq) {
 			arm7_9->set_special_dbgrq(target);
 		} else {
-			buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);	
+			buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
 			embeddedice_store_reg(dbg_ctrl);
 		}
 	}
@@ -1018,7 +1018,7 @@ int arm7_9_halt(target_t *target)
 	}
 
 	target->debug_reason = DBG_REASON_DBGRQ;
-	
+
 	return ERROR_OK;
 }
 
@@ -1050,9 +1050,9 @@ int arm7_9_debug_entry(target_t *target)
 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 	embeddedice_store_reg(dbg_ctrl);
-	
+
 	arm7_9_clear_halt(target);
-	
+
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
@@ -1067,7 +1067,7 @@ int arm7_9_debug_entry(target_t *target)
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	/* if the target is in Thumb state, change to ARM state */
 	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
 	{
@@ -1083,27 +1083,27 @@ int arm7_9_debug_entry(target_t *target)
 		/* Entered debug from ARM mode */
 		armv4_5->core_state = ARMV4_5_STATE_ARM;
 	}
-	
+
 	for (i = 0; i < 16; i++)
 		context_p[i] = &context[i];
 	/* save core registers (r0 - r15 of current core mode) */
 	arm7_9->read_core_regs(target, 0xffff, context_p);
 
 	arm7_9->read_xpsr(target, &cpsr, 0);
-	
+
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 		return retval;
-	
+
 	/* if the core has been executing in Thumb state, set the T bit */
 	if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
-		cpsr |= 0x20;	
-	
+		cpsr |= 0x20;
+
 	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
 	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
 	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
-	
+
 	armv4_5->core_mode = cpsr & 0x1f;
-	
+
 	if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
 	{
 		target->state = TARGET_UNKNOWN;
@@ -1112,7 +1112,7 @@ int arm7_9_debug_entry(target_t *target)
 	}
 
 	LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
-	
+
 	if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 	{
 		LOG_DEBUG("thumb state, applying fixups");
@@ -1139,7 +1139,7 @@ int arm7_9_debug_entry(target_t *target)
 
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
-	
+
 	for (i=0; i<=15; i++)
 	{
 		LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
@@ -1147,9 +1147,9 @@ int arm7_9_debug_entry(target_t *target)
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 	}
-	
+
 	LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
-	
+
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
 
@@ -1185,13 +1185,13 @@ int arm7_9_full_context(target_t *target)
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
 	LOG_DEBUG("-");
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
 
@@ -1204,19 +1204,19 @@ int arm7_9_full_context(target_t *target)
 		u32* reg_p[16];
 		int j;
 		int valid = 1;
-		
-		/* check if there are invalid registers in the current mode 
+
+		/* check if there are invalid registers in the current mode
 		 */
 		for (j = 0; j <= 16; j++)
 		{
 			if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
 				valid = 0;
 		}
-		
+
 		if (!valid)
 		{
 			u32 tmp_cpsr;
-			
+
 			/* change processor mode (and mask T bit) */
 			tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
 			tmp_cpsr |= armv4_5_number_to_mode(i);
@@ -1226,18 +1226,18 @@ int arm7_9_full_context(target_t *target)
 			for (j = 0; j < 15; j++)
 			{
 				if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
-				{	
+				{
 					reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
 					mask |= 1 << j;
 					ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
 					ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
 				}
 			}
-			
+
 			/* if only the PSR is invalid, mask is all zeroes */
 			if (mask)
 				arm7_9->read_core_regs(target, mask, reg_p);
-			
+
 			/* check if the PSR has to be read */
 			if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
 			{
@@ -1250,7 +1250,7 @@ int arm7_9_full_context(target_t *target)
 
 	/* restore processor mode (mask T bit) */
 	arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
-	
+
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
@@ -1262,27 +1262,27 @@ int arm7_9_restore_context(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	reg_t *reg; 
+	reg_t *reg;
 	armv4_5_core_reg_t *reg_arch_info;
 	enum armv4_5_mode current_mode = armv4_5->core_mode;
 	int i, j;
 	int dirty;
 	int mode_change;
-	
+
 	LOG_DEBUG("-");
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	if (arm7_9->pre_restore_context)
 		arm7_9->pre_restore_context(target);
-	
+
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
-		
+
 	/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
 	 * SYS shares registers with User, so we don't touch SYS
 	 */
@@ -1291,7 +1291,7 @@ int arm7_9_restore_context(target_t *target)
 		LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
 		dirty = 0;
 		mode_change = 0;
-		/* check if there are dirty registers in the current mode 
+		/* check if there are dirty registers in the current mode
 		*/
 		for (j = 0; j <= 16; j++)
 		{
@@ -1305,7 +1305,7 @@ int arm7_9_restore_context(target_t *target)
 					LOG_DEBUG("examining dirty reg: %s", reg->name);
 					if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
 						&& (reg_arch_info->mode != current_mode)
-						&& !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS)) 
+						&& !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
 						&& !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
 					{
 						mode_change = 1;
@@ -1318,7 +1318,7 @@ int arm7_9_restore_context(target_t *target)
 				}
 			}
 		}
-		
+
 		if (dirty)
 		{
 			u32 mask = 0x0;
@@ -1328,7 +1328,7 @@ int arm7_9_restore_context(target_t *target)
 			if (mode_change)
 			{
 				u32 tmp_cpsr;
-			
+
 				/* change processor mode (mask T bit) */
 				tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
 				tmp_cpsr |= armv4_5_number_to_mode(i);
@@ -1336,13 +1336,13 @@ int arm7_9_restore_context(target_t *target)
 				arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
 				current_mode = armv4_5_number_to_mode(i);
 			}
-			
+
 			for (j = 0; j <= 14; j++)
 			{
 				reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
 				reg_arch_info = reg->arch_info;
-				
-				
+
+
 				if (reg->dirty == 1)
 				{
 					regs[j] = buf_get_u32(reg->value, 0, 32);
@@ -1353,12 +1353,12 @@ int arm7_9_restore_context(target_t *target)
 					LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
 				}
 			}
-			
+
 			if (mask)
 			{
 				arm7_9->write_core_regs(target, mask, regs);
 			}
-			
+
 			reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
 			reg_arch_info = reg->arch_info;
 			if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
@@ -1368,12 +1368,12 @@ int arm7_9_restore_context(target_t *target)
 			}
 		}
 	}
-	
+
 	if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
 	{
 		/* restore processor mode (mask T bit) */
 		u32 tmp_cpsr;
-			
+
 		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
 		tmp_cpsr |= armv4_5_number_to_mode(i);
 		tmp_cpsr &= ~0x20;
@@ -1388,12 +1388,12 @@ int arm7_9_restore_context(target_t *target)
 		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
 		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 	}
-	
+
 	/* restore PC */
 	LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 	arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 	armv4_5->core_cache->reg_list[15].dirty = 0;
-			
+
 	if (arm7_9->post_restore_context)
 		arm7_9->post_restore_context(target);
 
@@ -1405,7 +1405,7 @@ int arm7_9_restart_core(struct target_s *target)
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-	
+
 	/* set RESTART instruction */
 	jtag_add_end_state(TAP_RTI);
 	if (arm7_9->need_bypass_before_restart) {
@@ -1413,7 +1413,7 @@ int arm7_9_restart_core(struct target_s *target)
 		arm_jtag_set_instr(jtag_info, 0xf, NULL);
 	}
 	arm_jtag_set_instr(jtag_info, 0x4, NULL);
-	
+
 	jtag_add_runtest(1, TAP_RTI);
 	return jtag_execute_queue();
 }
@@ -1421,7 +1421,7 @@ int arm7_9_restart_core(struct target_s *target)
 void arm7_9_enable_watchpoints(struct target_s *target)
 {
 	watchpoint_t *watchpoint = target->watchpoints;
-	
+
 	while (watchpoint)
 	{
 		if (watchpoint->set == 0)
@@ -1433,7 +1433,7 @@ void arm7_9_enable_watchpoints(struct target_s *target)
 void arm7_9_enable_breakpoints(struct target_s *target)
 {
 	breakpoint_t *breakpoint = target->breakpoints;
-	
+
 	/* set any pending breakpoints */
 	while (breakpoint)
 	{
@@ -1455,7 +1455,7 @@ void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
 			arm7_9_unset_breakpoint(target, breakpoint);
 		breakpoint = breakpoint->next;
 	}
-	
+
 	while (watchpoint)
 	{
 		if (watchpoint->set != 0)
@@ -1471,24 +1471,24 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 	breakpoint_t *breakpoint = target->breakpoints;
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 	int err;
-	
+
 	LOG_DEBUG("-");
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	if (!debug_execution)
 	{
 		target_free_all_working_areas(target);
 	}
-	
+
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	if (!current)
 		buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
-	
+
 	/* the front-end may request us not to handle breakpoints */
 	if (handle_breakpoints)
 	{
@@ -1496,14 +1496,14 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 		{
 			LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
 			arm7_9_unset_breakpoint(target, breakpoint);
-			
+
 			LOG_DEBUG("enable single-step");
 			arm7_9->enable_single_step(target);
-			
+
 			target->debug_reason = DBG_REASON_SINGLESTEP;
 
 			arm7_9_restore_context(target);
-			
+
 			if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 				arm7_9->branch_resume(target);
 			else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
@@ -1515,11 +1515,11 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 				LOG_ERROR("unhandled core state");
 				return ERROR_FAIL;
 			}
-				
+
 			buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
 			embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
 			err = arm7_9_execute_sys_speed(target);
-			
+
 			LOG_DEBUG("disable single-step");
 			arm7_9->disable_single_step(target);
 
@@ -1537,13 +1537,13 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 			arm7_9_set_breakpoint(target, breakpoint);
 		}
 	}
-	
+
 	/* enable any pending breakpoints and watchpoints */
 	arm7_9_enable_breakpoints(target);
 	arm7_9_enable_watchpoints(target);
-	
+
 	arm7_9_restore_context(target);
-	
+
 	if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 	{
 		arm7_9->branch_resume(target);
@@ -1557,18 +1557,18 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 		LOG_ERROR("unhandled core state");
 		return ERROR_FAIL;
 	}
-	
+
 	/* deassert DBGACK and INTDIS */
 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
 	/* INTDIS only when we really resume, not during debug execution */
 	if (!debug_execution)
 		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
 	embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
-	
+
 	arm7_9_restart_core(target);
-	
+
 	target->debug_reason = DBG_REASON_NOTHALTED;
-	
+
 	if (!debug_execution)
 	{
 		/* registers are now invalid */
@@ -1581,9 +1581,9 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 		target->state = TARGET_DEBUG_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 	}
-	
+
 	LOG_DEBUG("target resumed");
-	
+
 	return ERROR_OK;
 }
 
@@ -1591,7 +1591,7 @@ void arm7_9_enable_eice_step(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	/* setup an inverse breakpoint on the current PC
 	* - comparator 1 matches the current address
 	* - rangeout from comparator 1 is connected to comparator 0 rangein
@@ -1635,22 +1635,22 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
-	
+
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	if (!current)
 		buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
-	
+
 	/* the front-end may request us not to handle breakpoints */
 	if (handle_breakpoints)
 		if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
 			arm7_9_unset_breakpoint(target, breakpoint);
-	
+
 	target->debug_reason = DBG_REASON_SINGLESTEP;
 
 	arm7_9_restore_context(target);
-	
+
 	arm7_9->enable_single_step(target);
-	
+
 	if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 	{
 		arm7_9->branch_resume(target);
@@ -1664,15 +1664,15 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 		LOG_ERROR("unhandled core state");
 		return ERROR_FAIL;
 	}
-	
+
 	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 
 	err = arm7_9_execute_sys_speed(target);
 	arm7_9->disable_single_step(target);
-	
+
 	/* registers are now invalid */
 	armv4_5_invalidate_core_regs(target);
-	
+
 	if (err != ERROR_OK)
 	{
 		target->state = TARGET_UNKNOWN;
@@ -1681,10 +1681,10 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 		target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 		LOG_DEBUG("target stepped");
 	}
-	
+
 	if (breakpoint)
 		arm7_9_set_breakpoint(target, breakpoint);
-	
+
 	return err;
 
 }
@@ -1696,33 +1696,33 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
-	
+
 	enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
-	
+
 	if ((num < 0) || (num > 16))
 		return ERROR_INVALID_ARGUMENTS;
-	
+
 	if ((mode != ARMV4_5_MODE_ANY)
 			&& (mode != armv4_5->core_mode)
 			&& (reg_mode != ARMV4_5_MODE_ANY))
 	{
 		u32 tmp_cpsr;
-			
+
 		/* change processor mode (mask T bit) */
 		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
 		tmp_cpsr |= mode;
 		tmp_cpsr &= ~0x20;
 		arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
 	}
-	
+
 	if ((num >= 0) && (num <= 15))
 	{
 		/* read a normal core register */
 		reg_p[num] = &value;
-		
+
 		arm7_9->read_core_regs(target, 1 << num, reg_p);
 	}
 	else
@@ -1732,28 +1732,28 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
 		 */
 		armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
 		int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
-		
+
 		arm7_9->read_xpsr(target, &value, spsr);
 	}
-	
+
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
-		
+
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
 	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
-		
+
 	if ((mode != ARMV4_5_MODE_ANY)
 			&& (mode != armv4_5->core_mode)
 			&& (reg_mode != ARMV4_5_MODE_ANY))	{
 		/* restore processor mode (mask T bit) */
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 	}
-	
+
 	return ERROR_OK;
-	
+
 }
 
 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
@@ -1761,32 +1761,32 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
 	u32 reg[16];
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
-	
+
 	enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
 
 	if ((num < 0) || (num > 16))
 		return ERROR_INVALID_ARGUMENTS;
-	
+
 	if ((mode != ARMV4_5_MODE_ANY)
 			&& (mode != armv4_5->core_mode)
 			&& (reg_mode != ARMV4_5_MODE_ANY))	{
 		u32 tmp_cpsr;
-			
+
 		/* change processor mode (mask T bit) */
 		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
 		tmp_cpsr |= mode;
 		tmp_cpsr &= ~0x20;
 		arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
 	}
-	
+
 	if ((num >= 0) && (num <= 15))
 	{
 		/* write a normal core register */
 		reg[num] = value;
-		
+
 		arm7_9->write_core_regs(target, 1 << num, reg);
 	}
 	else
@@ -1796,24 +1796,24 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
 		*/
 		armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
 		int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
-		
+
 		/* if we're writing the CPSR, mask the T bit */
 		if (!spsr)
 			value &= ~0x20;
-		
+
 		arm7_9->write_xpsr(target, value, spsr);
 	}
-	
+
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-		
+
 	if ((mode != ARMV4_5_MODE_ANY)
 			&& (mode != armv4_5->core_mode)
 			&& (reg_mode != ARMV4_5_MODE_ANY))	{
 		/* restore processor mode (mask T bit) */
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 	}
-	
+
 	return jtag_execute_queue();
 }
 
@@ -1821,7 +1821,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	u32 reg[16];
 	int num_accesses = 0;
 	int thisrun_accesses;
@@ -1829,7 +1829,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 	u32 cpsr;
 	int retval;
 	int last_reg = 0;
-	
+
 	LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
 
 	if (target->state != TARGET_HALTED)
@@ -1844,11 +1844,11 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 
 	if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 		return ERROR_TARGET_UNALIGNED_ACCESS;
-	
+
 	/* load the base register with the address of the first word */
 	reg[0] = address;
 	arm7_9->write_core_regs(target, 0x1, reg);
-	
+
 	switch (size)
 	{
 		case 4:
@@ -1857,12 +1857,12 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 				u32 reg_list;
 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
-				
+
 				if (last_reg <= thisrun_accesses)
 					last_reg = thisrun_accesses;
-				
+
 				arm7_9->load_word_regs(target, reg_list);
-				
+
 				/* fast memory reads are only safe when the target is running
 				 * from a sufficiently high clock (32 kHz is usually too slow)
 				 */
@@ -1870,13 +1870,13 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 					arm7_9_execute_fast_sys_speed(target);
 				else
 					arm7_9_execute_sys_speed(target);
-									
+
 				arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
-				
+
 				/* advance buffer, count number of accesses */
 				buffer += thisrun_accesses * 4;
 				num_accesses += thisrun_accesses;
-			}	
+			}
 			break;
 		case 2:
 			while (num_accesses < count)
@@ -1884,7 +1884,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 				u32 reg_list;
 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
-				
+
 				for (i = 1; i <= thisrun_accesses; i++)
 				{
 					if (i > last_reg)
@@ -1898,13 +1898,13 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 					else
 						arm7_9_execute_sys_speed(target);
 				}
-				
+
 				arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
-				
+
 				/* advance buffer, count number of accesses */
 				buffer += thisrun_accesses * 2;
 				num_accesses += thisrun_accesses;
-			}	
+			}
 			break;
 		case 1:
 			while (num_accesses < count)
@@ -1912,7 +1912,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 				u32 reg_list;
 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
-				
+
 				for (i = 1; i <= thisrun_accesses; i++)
 				{
 					if (i > last_reg)
@@ -1926,20 +1926,20 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 					else
 						arm7_9_execute_sys_speed(target);
 				}
-				
+
 				arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
-				
+
 				/* advance buffer, count number of accesses */
 				buffer += thisrun_accesses * 1;
 				num_accesses += thisrun_accesses;
-			}	
+			}
 			break;
 		default:
 			LOG_ERROR("BUG: we shouldn't get here");
 			exit(-1);
 			break;
 	}
-	
+
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
 
@@ -1961,7 +1961,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 
 		return ERROR_TARGET_DATA_ABORT;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -1970,7 +1970,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
-	
+
 	u32 reg[16];
 	int num_accesses = 0;
 	int thisrun_accesses;
@@ -1995,15 +1995,15 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 
 	if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 		return ERROR_TARGET_UNALIGNED_ACCESS;
-	
+
 	/* load the base register with the address of the first word */
 	reg[0] = address;
 	arm7_9->write_core_regs(target, 0x1, reg);
-	
+
 	/* Clear DBGACK, to make sure memory fetches work as expected */
 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
 	embeddedice_store_reg(dbg_ctrl);
-	
+
 	switch (size)
 	{
 		case 4:
@@ -2012,7 +2012,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 				u32 reg_list;
 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
-				
+
 				for (i = 1; i <= thisrun_accesses; i++)
 				{
 					if (i > last_reg)
@@ -2020,11 +2020,11 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 					reg[i] = target_buffer_get_u32(target, buffer);
 					buffer += 4;
 				}
-				
+
 				arm7_9->write_core_regs(target, reg_list, reg);
-				
+
 				arm7_9->store_word_regs(target, reg_list);
-				
+
 				/* fast memory writes are only safe when the target is running
 				 * from a sufficiently high clock (32 kHz is usually too slow)
 				 */
@@ -2032,9 +2032,9 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 					arm7_9_execute_fast_sys_speed(target);
 				else
 					arm7_9_execute_sys_speed(target);
-				
+
 				num_accesses += thisrun_accesses;
-			}	
+			}
 			break;
 		case 2:
 			while (num_accesses < count)
@@ -2042,7 +2042,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 				u32 reg_list;
 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
-				
+
 				for (i = 1; i <= thisrun_accesses; i++)
 				{
 					if (i > last_reg)
@@ -2050,13 +2050,13 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 					reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
 					buffer += 2;
 				}
-				
+
 				arm7_9->write_core_regs(target, reg_list, reg);
-				
+
 				for (i = 1; i <= thisrun_accesses; i++)
 				{
 					arm7_9->store_hword_reg(target, i);
-					
+
 					/* fast memory writes are only safe when the target is running
 					 * from a sufficiently high clock (32 kHz is usually too slow)
 					 */
@@ -2065,9 +2065,9 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 					else
 						arm7_9_execute_sys_speed(target);
 				}
-				
+
 				num_accesses += thisrun_accesses;
-			}	
+			}
 			break;
 		case 1:
 			while (num_accesses < count)
@@ -2075,16 +2075,16 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 				u32 reg_list;
 				thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
 				reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
-				
+
 				for (i = 1; i <= thisrun_accesses; i++)
 				{
 					if (i > last_reg)
 						last_reg = i;
 					reg[i] = *buffer++ & 0xff;
 				}
-				
+
 				arm7_9->write_core_regs(target, reg_list, reg);
-				
+
 				for (i = 1; i <= thisrun_accesses; i++)
 				{
 					arm7_9->store_byte_reg(target, i);
@@ -2096,20 +2096,20 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 					else
 						arm7_9_execute_sys_speed(target);
 				}
-				
+
 				num_accesses += thisrun_accesses;
-			}	
+			}
 			break;
 		default:
 			LOG_ERROR("BUG: we shouldn't get here");
 			exit(-1);
 			break;
 	}
-	
+
 	/* Re-Set DBGACK */
 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 	embeddedice_store_reg(dbg_ctrl);
-	
+
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
 
@@ -2131,11 +2131,11 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 
 		return ERROR_TARGET_DATA_ABORT;
 	}
-	
+
 	return ERROR_OK;
 }
 
-static const u32 dcc_code[] = 
+static const u32 dcc_code[] =
 {
 	/* MRC      TST         BNE         MRC         STR         B */
 	0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
@@ -2150,7 +2150,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 	u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
 	u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
 	int i;
-	
+
 	if (!arm7_9->dcc_downloads)
 		return target->type->write_memory(target, address, 4, count, buffer);
 
@@ -2158,61 +2158,47 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 	if (!arm7_9->dcc_working_area)
 	{
 		u8 dcc_code_buf[6 * 4];
-		
+
 		/* make sure we have a working area */
 		if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
 		{
 			LOG_INFO("no working area available, falling back to memory writes");
 			return target->type->write_memory(target, address, 4, count, buffer);
 		}
-		
+
 		/* copy target instructions to target endianness */
 		for (i = 0; i < 6; i++)
 		{
 			target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
 		}
-		
+
 		/* write DCC code to working area */
 		target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
 	}
-	
+
 	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
 	armv4_5->core_cache->reg_list[0].valid = 1;
 	armv4_5->core_cache->reg_list[0].dirty = 1;
 	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
-	
+
 	int little=target->endianness==TARGET_LITTLE_ENDIAN;
 	if (count>2)
 	{
 		/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
-		   core function repeated. 
+		   core function repeated.
 		 */
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
 		buffer+=4;
-		
+
 		embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
 		u8 reg_addr = ice_reg->addr & 0x1f;
 		int chain_pos = ice_reg->jtag_info->chain_pos;
-		/* we want the compiler to duplicate the code, which it does not
-		 * do automatically.
-		 */
-		if (little)
-		{
-			for (i = 1; i < count - 1; i++)
-			{
-				embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
-				buffer += 4;
-			}
-		} else
-		{
-			for (i = 1; i < count - 1; i++)
-			{
-				embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
-				buffer += 4;
-			}
-		}
+
+		embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
+		buffer += (count-2)*4;
+
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
 	} else
 	{
@@ -2222,9 +2208,9 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 			buffer += 4;
 		}
 	}
-	
+
 	target_halt(target);
-	
+
 	for (i=0; i<100; i++)
 	{
 		target_poll(target);
@@ -2237,7 +2223,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 		LOG_ERROR("bulk write timed out, target not halted");
 		return ERROR_TARGET_TIMEOUT;
 	}
-	
+
 	/* restore target state */
 	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
 	armv4_5->core_cache->reg_list[0].valid = 1;
@@ -2249,7 +2235,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 	armv4_5->core_cache->reg_list[15].valid = 1;
 	armv4_5->core_cache->reg_list[15].dirty = 1;
 	armv4_5->core_state = core_state;
-	
+
 	return ERROR_OK;
 }
 
@@ -2259,7 +2245,7 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
 	armv4_5_algorithm_t armv4_5_info;
 	reg_param_t reg_params[2];
 	int retval;
-	
+
 	u32 arm7_9_crc_code[] = {
 		0xE1A02000,				/* mov		r2, r0 */
 		0xE3E00000,				/* mov		r0, #0xffffffff */
@@ -2287,28 +2273,28 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
 		0xEAFFFFFE,				/* b		end */
 		0x04C11DB7				/* CRC32XOR:	.word 0x04C11DB7 */
 	};
-	
+
 	int i;
-	
+
 	if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
 	{
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
-	
+
 	/* convert flash writing code into a buffer in target endianness */
 	for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
 		target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
-	
+
 	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
 	armv4_5_info.core_state = ARMV4_5_STATE_ARM;
-	
+
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
-	
+
 	buf_set_u32(reg_params[0].value, 0, 32, address);
 	buf_set_u32(reg_params[1].value, 0, 32, count);
-		
+
 	if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
 		crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
 	{
@@ -2318,14 +2304,14 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
 		target_free_working_area(target, crc_algorithm);
 		return retval;
 	}
-	
+
 	*checksum = buf_get_u32(reg_params[0].value, 0, 32);
-	
+
 	destroy_reg_param(&reg_params[0]);
 	destroy_reg_param(&reg_params[1]);
-	
+
 	target_free_working_area(target, crc_algorithm);
-	
+
 	return ERROR_OK;
 }
 
@@ -2336,7 +2322,7 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u
 	armv4_5_algorithm_t armv4_5_info;
 	int retval;
 	int i;
-	
+
 	u32 erase_check_code[] =
 	{
 						/* loop: */
@@ -2353,11 +2339,11 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u
 	{
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
-	
+
 	/* convert flash writing code into a buffer in target endianness */
 	for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
 		target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]);
-	
+
 	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
 	armv4_5_info.core_state = ARMV4_5_STATE_ARM;
@@ -2370,8 +2356,8 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u
 
 	init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 	buf_set_u32(reg_params[2].value, 0, 32, 0xff);
-	
-	if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, 
+
+	if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
 			erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
 	{
 		destroy_reg_param(&reg_params[0]);
@@ -2380,29 +2366,29 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u
 		target_free_working_area(target, erase_check_algorithm);
 		return 0;
 	}
-	
+
 	*blank = buf_get_u32(reg_params[2].value, 0, 32);
-	
+
 	destroy_reg_param(&reg_params[0]);
 	destroy_reg_param(&reg_params[1]);
 	destroy_reg_param(&reg_params[2]);
-	
+
 	target_free_working_area(target, erase_check_algorithm);
-	
+
 	return ERROR_OK;
 }
 
 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
 {
 	command_t *arm7_9_cmd;
-	
+
 	arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
 
 	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
 	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
-	
-	register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");	
-	
+
+	register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
+
 	register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
 	register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
 	register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
@@ -2415,9 +2401,9 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx)
 		COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
 
 	armv4_5_register_commands(cmd_ctx);
-	
+
 	etm_register_commands(cmd_ctx);
-	
+
 	return ERROR_OK;
 }
 
@@ -2435,33 +2421,33 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		command_print(cmd_ctx, "can't write registers while running");
 		return ERROR_OK;
 	}
-	
+
 	if (argc < 2)
 	{
 		command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
 		return ERROR_OK;
 	}
-	
+
 	value = strtoul(args[0], NULL, 0);
 	spsr = strtol(args[1], NULL, 0);
-	
+
 	/* if we're writing the CPSR, mask the T bit */
 	if (!spsr)
 		value &= ~0x20;
-	
+
 	arm7_9->write_xpsr(target, value, spsr);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		LOG_ERROR("JTAG error while writing to xpsr");
 		return retval;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -2480,30 +2466,30 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		command_print(cmd_ctx, "can't write registers while running");
 		return ERROR_OK;
 	}
-	
+
 	if (argc < 3)
 	{
 		command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
 		return ERROR_OK;
 	}
-	
+
 	value = strtoul(args[0], NULL, 0);
 	rotate = strtol(args[1], NULL, 0);
 	spsr = strtol(args[2], NULL, 0);
-		
+
 	arm7_9->write_xpsr_im8(target, value, rotate, spsr);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
 		return retval;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -2515,31 +2501,31 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
-		
+
 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 	{
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		command_print(cmd_ctx, "can't write registers while running");
 		return ERROR_OK;
 	}
-	
+
 	if (argc < 3)
 	{
 		command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
 		return ERROR_OK;
 	}
-	
+
 	num = strtol(args[0], NULL, 0);
 	mode = strtoul(args[1], NULL, 0);
 	value = strtoul(args[2], NULL, 0);
-	
+
 	arm7_9_write_core_reg(target, num, mode, value);
-	
+
 	return ERROR_OK;
 }
 
@@ -2548,7 +2534,7 @@ int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd,
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_ERROR("target not halted");
@@ -2560,13 +2546,13 @@ int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd,
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if (argc == 0)
 	{
 		command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
 		return ERROR_OK;
 	}
-	
+
 	if (strcmp("enable", args[0]) == 0)
 	{
 		if (arm7_9->sw_bkpts_use_wp)
@@ -2593,9 +2579,9 @@ int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd,
 	{
 		command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
 	}
-	
+
 	command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
-	
+
 	return ERROR_OK;
 }
 
@@ -2604,13 +2590,13 @@ int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
-	
+
 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 	{
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
 	{
 		arm7_9->force_hw_bkpts = 1;
@@ -2627,7 +2613,7 @@ int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char
 	{
 		command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
 	}
-		
+
 	command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
 
 	return ERROR_OK;
@@ -2638,13 +2624,13 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
-	
+
 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 	{
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if (argc > 0)
 	{
 		if (strcmp("enable", args[0]) == 0)
@@ -2660,7 +2646,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch
 			command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
 		}
 	}
-		
+
 	command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
 
 	return ERROR_OK;
@@ -2671,13 +2657,13 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx,
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
-	
+
 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 	{
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if (argc > 0)
 	{
 		if (strcmp("enable", args[0]) == 0)
@@ -2693,7 +2679,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx,
 			command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
 		}
 	}
-		
+
 	command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
 
 	return ERROR_OK;
@@ -2704,13 +2690,13 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
-	
+
 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 	{
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if (argc > 0)
 	{
 		if (strcmp("enable", args[0]) == 0)
@@ -2726,7 +2712,7 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
 			command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
 		}
 	}
-		
+
 	command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
 
 	return ERROR_OK;
@@ -2735,38 +2721,38 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 {
 	armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
-	
+
 	arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
-	
+
 	arm_jtag_setup_connection(&arm7_9->jtag_info);
 	arm7_9->wp_available = 2;
 	arm7_9->wp0_used = 0;
 	arm7_9->wp1_used = 0;
 	arm7_9->force_hw_bkpts = 0;
 	arm7_9->use_dbgrq = 0;
-	
+
 	arm7_9->etm_ctx = NULL;
 	arm7_9->has_single_step = 0;
 	arm7_9->has_monitor_mode = 0;
 	arm7_9->has_vector_catch = 0;
-	
+
 	arm7_9->debug_entry_from_reset = 0;
-	
+
 	arm7_9->dcc_working_area = NULL;
-	
+
 	arm7_9->fast_memory_access = fast_and_dangerous;
 	arm7_9->dcc_downloads = fast_and_dangerous;
-	
+
 	arm7_9->need_bypass_before_restart = 0;
-	
+
 	armv4_5->arch_info = arm7_9;
 	armv4_5->read_core_reg = arm7_9_read_core_reg;
 	armv4_5->write_core_reg = arm7_9_write_core_reg;
 	armv4_5->full_context = arm7_9_full_context;
-	
+
 	armv4_5_init_arch_info(target, armv4_5);
-	
+
 	target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
-	
+
 	return ERROR_OK;
 }
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 56368452..32e451a2 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -39,7 +39,7 @@
 
 #include <stdlib.h>
 
-bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] = 
+bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
 {
 	{"R", 1},
 	{"W", 1},
@@ -59,24 +59,24 @@ char* embeddedice_reg_list[] =
 {
 	"debug_ctrl",
 	"debug_status",
-	
+
 	"comms_ctrl",
 	"comms_data",
-	
+
 	"watch 0 addr value",
 	"watch 0 addr mask",
 	"watch 0 data value",
 	"watch 0 data mask",
 	"watch 0 control value",
 	"watch 0 control mask",
-	
+
 	"watch 1 addr value",
 	"watch 1 addr mask",
 	"watch 1 data value",
 	"watch 1 data mask",
 	"watch 1 control value",
 	"watch 1 control mask",
-	
+
 	"vector catch"
 };
 
@@ -99,26 +99,26 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
 	int num_regs;
 	int i;
 	int eice_version = 0;
-	
+
 	/* register a register arch-type for EmbeddedICE registers only once */
 	if (embeddedice_reg_arch_type == -1)
 		embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
-	
+
 	if (arm7_9->has_vector_catch)
 		num_regs = 17;
 	else
 		num_regs = 16;
-		
+
 	/* the actual registers are kept in two arrays */
 	reg_list = calloc(num_regs, sizeof(reg_t));
 	arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
-	
+
 	/* fill in values for the reg cache */
 	reg_cache->name = "EmbeddedICE registers";
 	reg_cache->next = NULL;
 	reg_cache->reg_list = reg_list;
 	reg_cache->num_regs = num_regs;
-	
+
 	/* set up registers */
 	for (i = 0; i < num_regs; i++)
 	{
@@ -134,7 +134,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
 		arch_info[i].addr = embeddedice_reg_arch_info[i];
 		arch_info[i].jtag_info = jtag_info;
 	}
-	
+
 	/* identify EmbeddedICE version by reading DCC control register */
 	embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
 	if ((retval=jtag_execute_queue())!=ERROR_OK)
@@ -147,9 +147,9 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
 		free(arch_info);
 		return NULL;
 	}
-	
+
 	eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
-	
+
 	switch (eice_version)
 	{
 		case 1:
@@ -162,7 +162,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
 			arm7_9->has_single_step = 1;
 			break;
 		case 3:
-			LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken"); 
+			LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
 			reg_list[EICE_DBG_CTRL].size = 6;
 			reg_list[EICE_DBG_STAT].size = 5;
 			arm7_9->has_single_step = 1;
@@ -193,7 +193,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
 		default:
 			LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}
-	
+
 	return reg_cache;
 }
 
@@ -202,12 +202,12 @@ int embeddedice_setup(target_t *target)
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
+
 	/* explicitly disable monitor mode */
 	if (arm7_9->has_monitor_mode)
 	{
 		reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
-		
+
 		embeddedice_read_reg(dbg_ctrl);
 		if ((retval=jtag_execute_queue())!=ERROR_OK)
 			return retval;
@@ -224,12 +224,12 @@ int embeddedice_get_reg(reg_t *reg)
 		LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
 		exit(-1);
 	}
-	
+
 	if (jtag_execute_queue() != ERROR_OK)
 	{
 		LOG_ERROR("register read failed");
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -243,9 +243,9 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 
 	jtag_add_end_state(TAP_RTI);
 	arm_jtag_scann(ice_reg->jtag_info, 0x2);
-	
+
 	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
-	
+
 	fields[0].device = ice_reg->jtag_info->chain_pos;
 	fields[0].num_bits = 32;
 	fields[0].out_value = reg->value;
@@ -255,7 +255,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 	fields[0].in_check_mask = NULL;
 	fields[0].in_handler = NULL;
 	fields[0].in_handler_priv = NULL;
-	
+
 	fields[1].device = ice_reg->jtag_info->chain_pos;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
@@ -277,18 +277,18 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 	fields[2].in_check_mask = NULL;
 	fields[2].in_handler = NULL;
 	fields[2].in_handler_priv = NULL;
-	
+
 	jtag_add_dr_scan(3, fields, -1);
-	
+
 	fields[0].in_value = reg->value;
 	jtag_set_check_value(fields+0, check_value, check_mask, NULL);
-	
+
 	/* when reading the DCC data register, leaving the address field set to
 	 * EICE_COMMS_DATA would read the register twice
 	 * reading the control register is safe
 	 */
 	buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
-	
+
 	jtag_add_dr_scan(3, fields, -1);
 
 	return ERROR_OK;
@@ -307,7 +307,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 	jtag_add_end_state(TAP_RTI);
 	arm_jtag_scann(jtag_info, 0x2);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-	
+
 	fields[0].device = jtag_info->chain_pos;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
@@ -317,7 +317,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 	fields[0].in_check_mask = NULL;
 	fields[0].in_handler = NULL;
 	fields[0].in_handler_priv = NULL;
-	
+
 	fields[1].device = jtag_info->chain_pos;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
@@ -339,9 +339,9 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 	fields[2].in_check_mask = NULL;
 	fields[2].in_handler = NULL;
 	fields[2].in_handler_priv = NULL;
-	
+
 	jtag_add_dr_scan(3, fields, -1);
-	
+
 	while (size > 0)
 	{
 		/* when reading the last item, set the register address to the DCC control reg,
@@ -349,21 +349,21 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 		 */
 		if (size == 1)
 			buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
-		
+
 		fields[0].in_handler = arm_jtag_buf_to_u32;
 		fields[0].in_handler_priv = data;
 		jtag_add_dr_scan(3, fields, -1);
-		
+
 		data++;
 		size--;
 	}
-	
+
 	return jtag_execute_queue();
 }
 
 int embeddedice_read_reg(reg_t *reg)
 {
-	return embeddedice_read_reg_w_check(reg, NULL, NULL);	
+	return embeddedice_read_reg_w_check(reg, NULL, NULL);
 }
 
 int embeddedice_set_reg(reg_t *reg, u32 value)
@@ -373,18 +373,18 @@ int embeddedice_set_reg(reg_t *reg, u32 value)
 		LOG_ERROR("BUG: error scheduling EmbeddedICE register write");
 		exit(-1);
 	}
-	
+
 	buf_set_u32(reg->value, 0, reg->size, value);
 	reg->valid = 1;
 	reg->dirty = 0;
-	
+
 	return ERROR_OK;
 }
 
 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
 {
 	embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
-	
+
 	if (jtag_execute_queue() != ERROR_OK)
 	{
 		LOG_ERROR("register write failed");
@@ -398,15 +398,15 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
 	embeddedice_reg_t *ice_reg = reg->arch_info;
 
 	LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
-	
+
 	jtag_add_end_state(TAP_RTI);
 	arm_jtag_scann(ice_reg->jtag_info, 0x2);
-	
+
 	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 
 	u8 reg_addr = ice_reg->addr & 0x1f;
 	embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
-	
+
 	return ERROR_OK;
 }
 
@@ -548,3 +548,14 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 
 	return ERROR_TARGET_TIMEOUT;
 }
+
+/* this is the inner loop of the open loop DCC write of data to target */
+void MINIDRIVER(embeddedice_write_dcc)(int chain_pos, int reg_addr, u8 *buffer, int little, int count)
+{
+	int i;
+	for (i = 0; i < count; i++)
+	{
+		embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+		buffer += 4;
+	}
+}
diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h
index 1ab667c1..a5929e18 100644
--- a/src/target/embeddedice.h
+++ b/src/target/embeddedice.h
@@ -52,7 +52,7 @@ enum
 enum
 {
 	EICE_DBG_CONTROL_ICEDIS = 5,
-	EICE_DBG_CONTROL_MONEN = 4,	
+	EICE_DBG_CONTROL_MONEN = 4,
 	EICE_DBG_CONTROL_INTDIS = 2,
 	EICE_DBG_CONTROL_DBGRQ = 1,
 	EICE_DBG_CONTROL_DBGACK = 0,
@@ -105,24 +105,26 @@ extern int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size);
 extern int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size);
 extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout);
 
-/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of 
+/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of
  * embeddedice_write_reg
  */
 static const int embeddedice_num_bits[]={32,5,1};
 static __inline__ void embeddedice_write_reg_inner(int chain_pos, int reg_addr, u32 value)
 {
 	u32 values[3];
-	
+
 	values[0]=value;
 	values[1]=reg_addr;
 	values[2]=1;
-	
-	jtag_add_dr_out(chain_pos, 
+
+	jtag_add_dr_out(chain_pos,
 			3,
 			embeddedice_num_bits,
 			values,
 			-1);
 }
 
+void embeddedice_write_dcc(int chain_pos, int reg_addr, u8 *buffer, int little, int count);
+
 
 #endif /* EMBEDDED_ICE_H */