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| author | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:48:22 +0000 |
|---|---|---|
| committer | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:48:22 +0000 |
| commit | 71af49ca7fb11b0bd0c1ba9578826f49288b68ef (patch) | |
| tree | 9ba8dd705f83aa44879bc7b5817ce40317f1fc28 /tcl/board/digi_connectcore_wi-9c.cfg | |
| parent | 86a7d813a165fda2816b8152342219b6c4ae2fc4 (diff) | |
| download | openocd+libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.gz openocd+libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.bz2 openocd+libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.xz openocd+libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.zip | |
Remove annoying end-of-line whitespace from tcl/* files
git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/board/digi_connectcore_wi-9c.cfg')
| -rw-r--r-- | tcl/board/digi_connectcore_wi-9c.cfg | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/tcl/board/digi_connectcore_wi-9c.cfg b/tcl/board/digi_connectcore_wi-9c.cfg index f8b89122..58f12a68 100644 --- a/tcl/board/digi_connectcore_wi-9c.cfg +++ b/tcl/board/digi_connectcore_wi-9c.cfg @@ -4,15 +4,15 @@ reset_config trst_and_srst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME ns9360 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # This config file was defaulting to big endian.. set _ENDIAN big } @@ -46,17 +46,17 @@ $_TARGETNAME configure -event reset-init { mww 0x90600104 0x33313333 mww 0xA0700000 0x00000001 # Enable the memory controller. mww 0xA0700024 0x00000006 # Set the refresh counter 6 - mww 0xA0700028 0x00000001 # + mww 0xA0700028 0x00000001 # mww 0xA0700030 0x00000001 # Set the precharge period mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles mww 0xA070003C 0x00000001 # tAPR mww 0xA0700040 0x00000005 # tDAL mww 0xA0700044 0x00000001 # tWR - mww 0xA0700048 0x00000006 # tRC 32 clock cycles + mww 0xA0700048 0x00000006 # tRC 32 clock cycles mww 0xA070004C 0x00000006 # tRFC 32 clock cycles mww 0xA0700054 0x00000001 # tRRD mww 0xA0700058 0x00000001 # tMRD - mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4) + mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4) mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5) mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6) mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7) @@ -79,11 +79,11 @@ $_TARGETNAME configure -event reset-init { mww 0xA0900000 0x00000002 mww 0xA0900000 0x00000002 # - mdw 0xA0900000 - mdw 0xA0900000 - mdw 0xA0900000 - mdw 0xA0900000 - mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 # mww 0xA0700024 0x00000030 # Set the refresh counter to 30 mww 0xA0700020 0x00000083 # Issue SDRAM MODE command |