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| author | David Brownell <dbrownell@users.sourceforge.net> | 2010-03-15 08:37:43 -0700 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2010-03-15 08:37:43 -0700 |
| commit | 96f9790279f74f39b35fc3ad09340fd03123180c (patch) | |
| tree | 672f5b717c5f6edf3f7e1377341e37cd7f6497ee /tcl/board/hitex_lpc2929.cfg | |
| parent | 4b964a81ca1423b808a056b457e3d458689d50fa (diff) | |
| download | openocd+libswd-96f9790279f74f39b35fc3ad09340fd03123180c.tar.gz openocd+libswd-96f9790279f74f39b35fc3ad09340fd03123180c.tar.bz2 openocd+libswd-96f9790279f74f39b35fc3ad09340fd03123180c.tar.xz openocd+libswd-96f9790279f74f39b35fc3ad09340fd03123180c.zip | |
rename jtag_khz as adapter_khz
Globally rename "jtag_khz" as "adapter_khz", and move it out of the "jtag"
command group ... it needs to be used with non-JTAG transports
Includes a migration aid (in jtag/startup.tcl) so that old user scripts
won't break. That aid should Sunset in about a year. (We may want to
update it to include a nag message too.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'tcl/board/hitex_lpc2929.cfg')
| -rw-r--r-- | tcl/board/hitex_lpc2929.cfg | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg index 7d06f745..35cc7d0b 100644 --- a/tcl/board/hitex_lpc2929.cfg +++ b/tcl/board/hitex_lpc2929.cfg @@ -7,7 +7,7 @@ jtag_ntrst_delay 1 # Maximum of 1/8 of clock frequency (XTAL = 16 MHz). # Adaptive clocking through RTCK is not supported. -jtag_khz 2000 +adapter_khz 2000 # Target device: LPC29xx with ETB # The following variables are used by the LPC2900 script: @@ -24,7 +24,7 @@ $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work- # Event handlers $_TARGETNAME configure -event reset-start { # Back to the slow JTAG clock - jtag_khz 2000 + adapter_khz 2000 } # External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB) @@ -46,7 +46,7 @@ $_TARGETNAME configure -event reset-init { mww 0xFFFF8070 0x02000000 # SYS_CLK_CONF: PLL # Increase JTAG speed - jtag_khz 6000 + adapter_khz 6000 # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7) mww 0xE0001138 0x0000001F # P1.14 = D0 |