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author | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:48:22 +0000 |
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committer | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:48:22 +0000 |
commit | 71af49ca7fb11b0bd0c1ba9578826f49288b68ef (patch) | |
tree | 9ba8dd705f83aa44879bc7b5817ce40317f1fc28 /tcl/board/imx27ads.cfg | |
parent | 86a7d813a165fda2816b8152342219b6c4ae2fc4 (diff) | |
download | openocd+libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.gz openocd+libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.bz2 openocd+libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.xz openocd+libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.zip |
Remove annoying end-of-line whitespace from tcl/* files
git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/board/imx27ads.cfg')
-rw-r--r-- | tcl/board/imx27ads.cfg | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/tcl/board/imx27ads.cfg b/tcl/board/imx27ads.cfg index dc0de4a6..664b4705 100644 --- a/tcl/board/imx27ads.cfg +++ b/tcl/board/imx27ads.cfg @@ -24,52 +24,52 @@ proc imx27ads_init { } { # ======================================== # Configure DDR on CSD0 -- initial reset # ======================================== - mww 0xD8001010 0x00000008 + mww 0xD8001010 0x00000008 # ======================================== - # Configure PSRAM on CS5 + # Configure PSRAM on CS5 # ======================================== mww 0xd8002050 0x0000dcf6 - mww 0xd8002054 0x444a4541 - mww 0xd8002058 0x44443302 + mww 0xd8002054 0x444a4541 + mww 0xd8002058 0x44443302 # ======================================== # Configure16 bit NorFlash on CS0 # ======================================== - mww 0xd8002000 0x0000CC03 - mww 0xd8002004 0xa0330D01 - mww 0xd8002008 0x00220800 + mww 0xd8002000 0x0000CC03 + mww 0xd8002004 0xa0330D01 + mww 0xd8002008 0x00220800 # ======================================== - # Configure CPLD on CS4 + # Configure CPLD on CS4 # ======================================== - mww 0xd8002040 0x0000DCF6 - mww 0xd8002044 0x444A4541 - mww 0xd8002048 0x44443302 + mww 0xd8002040 0x0000DCF6 + mww 0xd8002044 0x444A4541 + mww 0xd8002048 0x44443302 # ======================================== - # Configure DDR on CSD0 -- wait 5000 cycle + # Configure DDR on CSD0 -- wait 5000 cycle # ======================================== - mww 0x10027828 0x55555555 - mww 0x10027830 0x55555555 - mww 0x10027834 0x55555555 - mww 0x10027838 0x00005005 - mww 0x1002783C 0x15555555 + mww 0x10027828 0x55555555 + mww 0x10027830 0x55555555 + mww 0x10027834 0x55555555 + mww 0x10027838 0x00005005 + mww 0x1002783C 0x15555555 - mww 0xD8001010 0x00000004 + mww 0xD8001010 0x00000004 - mww 0xD8001004 0x00795729 + mww 0xD8001004 0x00795729 - mww 0xD8001000 0x92200000 + mww 0xD8001000 0x92200000 mww 0xA0000F00 0x0 - mww 0xD8001000 0xA2200000 + mww 0xD8001000 0xA2200000 mww 0xA0000F00 0x0 mww 0xA0000F00 0x0 - mww 0xD8001000 0xB2200000 + mww 0xD8001000 0xB2200000 mwb 0xA0000033 0xFF mwb 0xA1000000 0xAA - mww 0xD8001000 0x82228085 + mww 0xD8001000 0x82228085 } |