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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-10-25 18:29:17 +0100 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-10-25 22:15:57 +0100 |
| commit | a07422c26cb0a659c7615d6c0aa2cf09d8a48829 (patch) | |
| tree | 6acf5287811133833ae4f6eb641d5cc95a514eb9 /tcl/board/mini2440.cfg | |
| parent | d785f552ee034aedb26aefc3e47e5c78cdcce065 (diff) | |
| download | openocd+libswd-a07422c26cb0a659c7615d6c0aa2cf09d8a48829.tar.gz openocd+libswd-a07422c26cb0a659c7615d6c0aa2cf09d8a48829.tar.bz2 openocd+libswd-a07422c26cb0a659c7615d6c0aa2cf09d8a48829.tar.xz openocd+libswd-a07422c26cb0a659c7615d6c0aa2cf09d8a48829.zip | |
fix syntax of mww phys.
Diffstat (limited to 'tcl/board/mini2440.cfg')
| -rw-r--r-- | tcl/board/mini2440.cfg | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 29819501..90acafa0 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -177,10 +177,10 @@ proc init_2440 { } { # usb clock are off 12mHz xtal #----------------------------------------------- - arm920t mww phys 0x4C000014 0x00000005 # Clock Divider control Reg - arm920t mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register - arm920t mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg - arm920t mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg + mww phys 0x4C000014 0x00000005 # Clock Divider control Reg + mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register + mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg + mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg #----------------------------------------------- # Configure Memory controller @@ -188,45 +188,45 @@ proc init_2440 { } { # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7 #----------------------------------------------- - arm920t mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width - arm920t mww phys 0x48000010 0x00001112 # BANKCON4 - ? - arm920t mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM - arm920t mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM - arm920t mww phys 0x48000024 0x008E04EB # REFRESH - DRAM - arm920t mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM - arm920t mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM - arm920t mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM + mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width + mww phys 0x48000010 0x00001112 # BANKCON4 - ? + mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM + mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM + mww phys 0x48000024 0x008E04EB # REFRESH - DRAM + mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM + mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM + mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM #----------------------------------------------- # Now port configuration for enables for memory # and other stuff. #----------------------------------------------- - arm920t mww phys 0x56000000 0x007FFFFF # GPACON + mww phys 0x56000000 0x007FFFFF # GPACON - arm920t mww phys 0x56000010 0x00295559 # GPBCON - arm920t mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE) - arm920t mww phys 0x56000014 0x000007C2 # GPBDAT + mww phys 0x56000010 0x00295559 # GPBCON + mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE) + mww phys 0x56000014 0x000007C2 # GPBDAT - arm920t mww phys 0x56000020 0xAAAAA6AA # GPCCON - arm920t mww phys 0x56000028 0x0000FFFF # GPCUP - arm920t mww phys 0x56000024 0x00000020 # GPCDAT + mww phys 0x56000020 0xAAAAA6AA # GPCCON + mww phys 0x56000028 0x0000FFFF # GPCUP + mww phys 0x56000024 0x00000020 # GPCDAT - arm920t mww phys 0x56000030 0xAAAAAAAA # GPDCON - arm920t mww phys 0x56000038 0x0000FFFF # GPDUP + mww phys 0x56000030 0xAAAAAAAA # GPDCON + mww phys 0x56000038 0x0000FFFF # GPDUP - arm920t mww phys 0x56000040 0xAAAAAAAA # GPECON - arm920t mww phys 0x56000048 0x0000FFFF # GPEUP + mww phys 0x56000040 0xAAAAAAAA # GPECON + mww phys 0x56000048 0x0000FFFF # GPEUP - arm920t mww phys 0x56000050 0x00001555 # GPFCON - arm920t mww phys 0x56000058 0x0000007F # GPFUP - arm920t mww phys 0x56000054 0x00000000 # GPFDAT + mww phys 0x56000050 0x00001555 # GPFCON + mww phys 0x56000058 0x0000007F # GPFUP + mww phys 0x56000054 0x00000000 # GPFDAT - arm920t mww phys 0x56000060 0x00150114 # GPGCON - arm920t mww phys 0x56000068 0x0000007F # GPGUP + mww phys 0x56000060 0x00150114 # GPGCON + mww phys 0x56000068 0x0000007F # GPGUP - arm920t mww phys 0x56000070 0x0015AAAA # GPHCON - arm920t mww phys 0x56000078 0x000003FF # GPGUP + mww phys 0x56000070 0x0015AAAA # GPHCON + mww phys 0x56000078 0x000003FF # GPGUP } |