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author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-10 08:06:22 +0000 |
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committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-10 08:06:22 +0000 |
commit | b4acbee47fcb29afc9958b4a9e74b9916a415dec (patch) | |
tree | b31f9d6de90f30fe61bc10860e2c901209e38b86 /tcl/board | |
parent | 7b5ddb4a58f31cc63f626b7ffb41c0b958540026 (diff) | |
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michal smulski <michal.smulski@ooma.com> telo target/board scripts
git-svn-id: svn://svn.berlios.de/openocd/trunk@2683 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/board')
-rw-r--r-- | tcl/board/telo.cfg | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/tcl/board/telo.cfg b/tcl/board/telo.cfg new file mode 100644 index 00000000..d740db2e --- /dev/null +++ b/tcl/board/telo.cfg @@ -0,0 +1,54 @@ +source [find target/c100.cfg] +# basic register defintion for C100 +source [find target/c100regs.tcl] +# board-config info +source [find target/c100config.tcl] +# C100 helper functions +source [find target/c100helper.tcl] + + +# Telo board & C100 support trst and srst +# however openocd does not support +# 1. setting srst reset pulse width +# 2. setting delay between srst pulse and JTAG access +# This really makes the srst useless for now. +reset_config trst_and_srst separate + + + +# issue telnet: reset init +# issue gdb: monitor reset init +$_TARGETNAME configure -event reset-init { + jtag_khz 100 + # setup GPIO used as control signals for C100 + setupGPIO + # This will allow acces to lower 8MB or NOR + lowGPIO5 + # setup NOR size,timing,etc. + setupNOR + # setup internals + PLL + DDR2 + initC100 + #turn up the JTAG speed + jtag_khz 3000 + puts "JTAG speek now 3MHz" + puts "type helpC100 to get help on C100" +} + +$_TARGETNAME configure -event reset-deassert-post { + # Force target into ARM state. +# soft_reset_halt # not implemented on ARM11 + puts "Detected SRSRT asserted on C100.CPU" + +} + +proc power_restore {} { puts "Sensed power restore. No action." } +proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." } + + +# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus +# it's really 16MB but the upper 8mb is controller via gpio +# openocd does not support 'complex reads/writes' to NOR +flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME + +# writing data to memory does not work without this +memwrite burst disable
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