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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-04-09 18:06:36 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-04-09 19:18:03 +0200 |
| commit | ba71e8c521a7e7c1652560f580f81d564e613508 (patch) | |
| tree | 2b579f49b454552776b632d810e995aa041e7820 /tcl/chip/atmel/at91/at91sam9_sdramc.cfg | |
| parent | 28e6dcee85ffdc5af0c630b0aca4e2087d95bca9 (diff) | |
| download | openocd+libswd-ba71e8c521a7e7c1652560f580f81d564e613508.tar.gz openocd+libswd-ba71e8c521a7e7c1652560f580f81d564e613508.tar.bz2 openocd+libswd-ba71e8c521a7e7c1652560f580f81d564e613508.tar.xz openocd+libswd-ba71e8c521a7e7c1652560f580f81d564e613508.zip | |
at91: add chip register definition and generic init support
for
- pio
- pmc
- rstc
- wdt
- sdramc
- smc
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
Diffstat (limited to 'tcl/chip/atmel/at91/at91sam9_sdramc.cfg')
| -rw-r--r-- | tcl/chip/atmel/at91/at91sam9_sdramc.cfg | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/tcl/chip/atmel/at91/at91sam9_sdramc.cfg b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg new file mode 100644 index 00000000..dbca497b --- /dev/null +++ b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg @@ -0,0 +1,66 @@ + +# SDRAM Controller (SDRAMC) registers +set AT91_SDRAMC_MR [expr ($AT91_SDRAMC + 0x00)] ;# SDRAM Controller Mode Register +set AT91_SDRAMC_MODE [expr (0xf << 0)] ;# Command Mode +set AT91_SDRAMC_MODE_NORMAL 0 +set AT91_SDRAMC_MODE_NOP 1 +set AT91_SDRAMC_MODE_PRECHARGE 2 +set AT91_SDRAMC_MODE_LMR 3 +set AT91_SDRAMC_MODE_REFRESH 4 +set AT91_SDRAMC_MODE_EXT_LMR 5 +set AT91_SDRAMC_MODE_DEEP 6 + +set AT91_SDRAMC_TR [expr ($AT91_SDRAMC + 0x04)] ;# SDRAM Controller Refresh Timer Register +set AT91_SDRAMC_COUNT [expr (0xfff << 0)] ;# Refresh Timer Counter + +set AT91_SDRAMC_CR [expr ($AT91_SDRAMC + 0x08)] ;# SDRAM Controller Configuration Register +set AT91_SDRAMC_NC [expr (3 << 0)] ;# Number of Column Bits +set AT91_SDRAMC_NC_8 [expr (0 << 0)] +set AT91_SDRAMC_NC_9 [expr (1 << 0)] +set AT91_SDRAMC_NC_10 [expr (2 << 0)] +set AT91_SDRAMC_NC_11 [expr (3 << 0)] +set AT91_SDRAMC_NR [expr (3 << 2)] ;# Number of Row Bits +set AT91_SDRAMC_NR_11 [expr (0 << 2)] +set AT91_SDRAMC_NR_12 [expr (1 << 2)] +set AT91_SDRAMC_NR_13 [expr (2 << 2)] +set AT91_SDRAMC_NB [expr (1 << 4)] ;# Number of Banks +set AT91_SDRAMC_NB_2 [expr (0 << 4)] +set AT91_SDRAMC_NB_4 [expr (1 << 4)] +set AT91_SDRAMC_CAS [expr (3 << 5)] ;# CAS Latency +set AT91_SDRAMC_CAS_1 [expr (1 << 5)] +set AT91_SDRAMC_CAS_2 [expr (2 << 5)] +set AT91_SDRAMC_CAS_3 [expr (3 << 5)] +set AT91_SDRAMC_DBW [expr (1 << 7)] ;# Data Bus Width +set AT91_SDRAMC_DBW_32 [expr (0 << 7)] +set AT91_SDRAMC_DBW_16 [expr (1 << 7)] +set AT91_SDRAMC_TWR [expr (0xf << 8)] ;# Write Recovery Delay +set AT91_SDRAMC_TRC [expr (0xf << 12)] ;# Row Cycle Delay +set AT91_SDRAMC_TRP [expr (0xf << 16)] ;# Row Precharge Delay +set AT91_SDRAMC_TRCD [expr (0xf << 20)] ;# Row to Column Delay +set AT91_SDRAMC_TRAS [expr (0xf << 24)] ;# Active to Precharge Delay +set AT91_SDRAMC_TXSR [expr (0xf << 28)] ;# Exit Self Refresh to Active Delay + +set AT91_SDRAMC_LPR [expr ($AT91_SDRAMC + 0x10)] ;# SDRAM Controller Low Power Register +set AT91_SDRAMC_LPCB [expr (3 << 0)] ;# Low-power Configurations +set AT91_SDRAMC_LPCB_DISABLE 0 +set AT91_SDRAMC_LPCB_SELF_REFRESH 1 +set AT91_SDRAMC_LPCB_POWER_DOWN 2 +set AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 +set AT91_SDRAMC_PASR [expr (7 << 4)] ;# Partial Array Self Refresh +set AT91_SDRAMC_TCSR [expr (3 << 8)] ;# Temperature Compensated Self Refresh +set AT91_SDRAMC_DS [expr (3 << 10)] ;# Drive Strength +set AT91_SDRAMC_TIMEOUT [expr (3 << 12)] ;# Time to define when Low Power Mode is enabled +set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr (0 << 12)] +set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr (1 << 12)] +set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr (2 << 12)] + +set AT91_SDRAMC_IER [expr ($AT91_SDRAMC + 0x14)] ;# SDRAM Controller Interrupt Enable Register +set AT91_SDRAMC_IDR [expr ($AT91_SDRAMC + 0x18)] ;# SDRAM Controller Interrupt Disable Register +set AT91_SDRAMC_IMR [expr ($AT91_SDRAMC + 0x1C)] ;# SDRAM Controller Interrupt Mask Register +set AT91_SDRAMC_ISR [expr ($AT91_SDRAMC + 0x20)] ;# SDRAM Controller Interrupt Status Register +set AT91_SDRAMC_RES [expr (1 << 0)] ;# Refresh Error Status + +set AT91_SDRAMC_MDR [expr ($AT91_SDRAMC + 0x24)] ;# SDRAM Memory Device Register +set AT91_SDRAMC_MD [expr (3 << 0)] ;# Memory Device Type +set AT91_SDRAMC_MD_SDRAM 0 +set AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 |