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author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-04-09 18:06:36 +0200 |
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committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-04-09 19:18:03 +0200 |
commit | ba71e8c521a7e7c1652560f580f81d564e613508 (patch) | |
tree | 2b579f49b454552776b632d810e995aa041e7820 /tcl/chip/atmel/at91/sam9_smc.cfg | |
parent | 28e6dcee85ffdc5af0c630b0aca4e2087d95bca9 (diff) | |
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at91: add chip register definition and generic init support
for
- pio
- pmc
- rstc
- wdt
- sdramc
- smc
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
Diffstat (limited to 'tcl/chip/atmel/at91/sam9_smc.cfg')
-rw-r--r-- | tcl/chip/atmel/at91/sam9_smc.cfg | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/tcl/chip/atmel/at91/sam9_smc.cfg b/tcl/chip/atmel/at91/sam9_smc.cfg new file mode 100644 index 00000000..db943cb2 --- /dev/null +++ b/tcl/chip/atmel/at91/sam9_smc.cfg @@ -0,0 +1,55 @@ +# Setup register +# +# ncs_read_setup +# nrd_setup +# ncs_write_setup +# set nwe_setup +# +# +# Pulse register +# +# ncs_read_pulse +# nrd_pulse +# ncs_write_pulse +# nwe_pulse +# +# +# Cycle register +# +# read_cycle 0 +# write_cycle 0 +# +# +# Mode register +# +# mode +# tdf_cycles +proc sam9_smc_config { cs smc_config } { + ;# Setup Register for CS n + set AT91_SMC_SETUP [expr ($::AT91_SMC + 0x00 + ((cs)*0x10))] + set val [expr ($smc_config(nwe_setup) << 0)] + set val [expr ($val | $smc_config(ncs_write_setup) << 8] + set val [expr ($val | $smc_config(nrd_setup)) << 16] + set val [expr ($val | $smc_config(ncs_read_setup) << 24] + mww $AT91_SMC_SETUP $val + + ;# Pulse Register for CS n + set AT91_SMC_PULSE [expr ($::AT91_SMC + 0x04 + ((cs)*0x10))] + set val [expr ($smc_config(nwe_pulse) << 0)] + set val [expr ($val | $smc_config(ncs_write_pulse) << 8] + set val [expr ($val | $smc_config(nrd_pulse) << 16] + set val [expr ($val | $smc_config(ncs_read_pulse) << 24] + mww $AT91_SMC_PULSE $val + + ;# Cycle Register for CS n + set AT91_SMC_CYCLE [expr ($::AT91_SMC + 0x08 + ((cs)*0x10))] + set val [expr ($smc_config(write_cycle) << 0)] + set val [expr ($val | $smc_config(read_cycle) << 16] + mww $AT91_SMC_CYCLE $val + + ;# Mode Register for CS n + set AT91_SMC_MODE [expr ($::AT91_SMC + 0x0c + ((cs)*0x10))] + set val [expr ($smc_config(mode) << 0)] + set val [expr ($val | $smc_config(tdf_cycles) << 16] + mww $AT91_SMC_MODE $val +} |