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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-03-02 12:57:03 +0100 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-03-03 22:49:46 +0100 |
| commit | e941805713fd2ad8b7f9740ae789b8a1f5b645ff (patch) | |
| tree | b7f5017e4ed09e7eefa124c1e11f316010f848de /tcl/target/at91sam9g20.cfg | |
| parent | 0eed61b7c4cb31338562db426cea0d1a999e0d9f (diff) | |
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at91sam9: factorise cpu support
all at91sam9 are nearly the same except sram and soc name
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
Diffstat (limited to 'tcl/target/at91sam9g20.cfg')
| -rw-r--r-- | tcl/target/at91sam9g20.cfg | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tcl/target/at91sam9g20.cfg b/tcl/target/at91sam9g20.cfg new file mode 100644 index 00000000..8a2e69b9 --- /dev/null +++ b/tcl/target/at91sam9g20.cfg @@ -0,0 +1,22 @@ +###################################### +# Target: Atmel AT91SAM9G20 +###################################### + +if { [info exists CHIPNAME] } { + set AT91_CHIPNAME $CHIPNAME +} else { + set AT91_CHIPNAME at91sam9g20 +} + +source [find target/at91sam9.cfg] + +# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock). + +jtag_rclk 5 + +# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The +# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000. +# Both areas are 16 kB long. + +#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1 +$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1 |