diff options
| author | Laurent Charpentier <laurent_pubs@yahoo.com> | 2011-06-06 11:51:38 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind@fierce.(none)> | 2011-06-08 07:19:39 +0200 |
| commit | 01c0ffe98f87e35f21b8f392b6432d4190d1eb43 (patch) | |
| tree | 73f48d0780079df1b3b747abd799ad7fe61fc1a3 /tcl/target | |
| parent | 33f9bec9ec5fe370e7a1398c53a7e97409f669ba (diff) | |
| download | openocd+libswd-01c0ffe98f87e35f21b8f392b6432d4190d1eb43.tar.gz openocd+libswd-01c0ffe98f87e35f21b8f392b6432d4190d1eb43.tar.bz2 openocd+libswd-01c0ffe98f87e35f21b8f392b6432d4190d1eb43.tar.xz openocd+libswd-01c0ffe98f87e35f21b8f392b6432d4190d1eb43.zip | |
Added configuration file for stm32f2xxx.
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/stm32f2xxx.cfg | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/tcl/target/stm32f2xxx.cfg b/tcl/target/stm32f2xxx.cfg new file mode 100644 index 00000000..9ebc00f3 --- /dev/null +++ b/tcl/target/stm32f2xxx.cfg @@ -0,0 +1,56 @@ +# script for stm32f2xxx + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f2xxx +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +jtag_khz 1000 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0033 + # Section 32.6.3 - corresponds to Cortex-M3 r2p0 + set _CPUTAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0033 + # Section 32.6.2 + # + set _BSTAPID 0x06411041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f2xxx 0 0 0 0 $_TARGETNAME + |