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| author | David Brownell <dbrownell@users.sourceforge.net> | 2010-02-15 13:39:16 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2010-02-15 13:39:16 -0800 |
| commit | 58699923148fa1e0bc3eee4308e351cedecf296a (patch) | |
| tree | 6f13d6d0baa952247e436d420e8532ad734555b8 /tcl/target | |
| parent | 52d4ba3467134a1489583dbb6d6de3002f0f76fa (diff) | |
| download | openocd+libswd-58699923148fa1e0bc3eee4308e351cedecf296a.tar.gz openocd+libswd-58699923148fa1e0bc3eee4308e351cedecf296a.tar.bz2 openocd+libswd-58699923148fa1e0bc3eee4308e351cedecf296a.tar.xz openocd+libswd-58699923148fa1e0bc3eee4308e351cedecf296a.zip | |
LPC1768.cfg -- partial fixes for bogus reset-init handler
Cortex-M targets don't support ARM instructions.
Leave the NVIC.VTOR setup alone, but comment how the whole
routine looks like one big bug...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/lpc1768.cfg | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg index 9a813f5b..f0093ad4 100644 --- a/tcl/target/lpc1768.cfg +++ b/tcl/target/lpc1768.cfg @@ -33,11 +33,11 @@ target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNA # LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM) $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0 +# REVISIT is there any good reason to have this reset-init event handler?? +# Normally they should set up (board-specific) clocking then probe the flash... $_TARGETNAME configure -event reset-init { - # Force target into ARM state - arm core_state arm - #do not remap 0x0000-0x0020 to anything but the flash -# mwb 0xE01FC040 0x01 + # Force NVIC.VTOR to point to flash at 0 ... + # WHY? This is it's reset value; we run right after reset!! mwb 0xE000ED08 0x00 } |