diff options
| author | Marek Vasut <marek.vasut@gmail.com> | 2010-10-29 02:57:32 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut@gmail.com> | 2010-11-05 11:25:57 +0100 |
| commit | d5b9c7998c43ee783c224035002cf32f062b0e2b (patch) | |
| tree | 0f2bcca04c9d4e4ca194d27c0782c4616fb90291 /tcl/target | |
| parent | 1fa91f336ae35a0b7b127c81c46ff9b5041e088e (diff) | |
| download | openocd+libswd-d5b9c7998c43ee783c224035002cf32f062b0e2b.tar.gz openocd+libswd-d5b9c7998c43ee783c224035002cf32f062b0e2b.tar.bz2 openocd+libswd-d5b9c7998c43ee783c224035002cf32f062b0e2b.tar.xz openocd+libswd-d5b9c7998c43ee783c224035002cf32f062b0e2b.zip | |
CortexA8: Introduce Freescale i.MX51 variant
This patch introduces support for Cortex A8 based Freescale i.MX51 CPU. This CPU
has the Debug Access Port located at a different address (0x60008000) than TI
OMAP3 series of CPUs.
i.MX51 configuration file based on OMAP3 configuration file and an email from
Alan Carvalho de Assis <acassis@gmail.com>.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/imx51.cfg | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg new file mode 100644 index 00000000..b1390ec2 --- /dev/null +++ b/tcl/target/imx51.cfg @@ -0,0 +1,51 @@ +# Freescale i.MX51 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx51 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID ] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x1ba00477 +} + +jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_DAP_TAPID + +# SDMA / no IDCODE +jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf + +# SJC +if { [info exists SJC_TAPID ] } { + set _SJC_TAPID SJC_TAPID +} else { + set _SJC_TAPID 0x0190c01d +} + +jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \ + -expected-id $_SJC_TAPID -ignore-version + +# GDB target: Cortex-A8, using DAP +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP + +# some TCK tycles are required to activate the DEBUG power domain +jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100" + +# have the DAP "always" be active +jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP" + +proc imx51_dbginit {target} { + # General Cortex A8 debug initialisation + cortex_a8 dbginit +} + +# Slow speed to be sure it will work +jtag_rclk 1000 +$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 } + +$_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME" |