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| author | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-13 13:54:53 +0000 |
|---|---|---|
| committer | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-13 13:54:53 +0000 |
| commit | 59b295dbbef33ba4d59adb67bcfb81e7463b95d4 (patch) | |
| tree | acadeea24a41221f7b76177f260a6b6ee522a332 /tcl | |
| parent | 720c39ba2fae188865a725728930e1e73d6eadf6 (diff) | |
| download | openocd+libswd-59b295dbbef33ba4d59adb67bcfb81e7463b95d4.tar.gz openocd+libswd-59b295dbbef33ba4d59adb67bcfb81e7463b95d4.tar.bz2 openocd+libswd-59b295dbbef33ba4d59adb67bcfb81e7463b95d4.tar.xz openocd+libswd-59b295dbbef33ba4d59adb67bcfb81e7463b95d4.zip | |
Audrius Urmanavičius [didele.deze@gmail.com]:
Add flash programming support for NXP LPC1700 cortex_m3 based family
git-svn-id: svn://svn.berlios.de/openocd/trunk@2579 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/board/keil_mcb1700.cfg | 8 | ||||
| -rw-r--r-- | tcl/target/lpc1768.cfg | 49 |
2 files changed, 57 insertions, 0 deletions
diff --git a/tcl/board/keil_mcb1700.cfg b/tcl/board/keil_mcb1700.cfg new file mode 100644 index 00000000..23e4e567 --- /dev/null +++ b/tcl/board/keil_mcb1700.cfg @@ -0,0 +1,8 @@ +# +# Keil MCB1700 eval board +# +# http://www.keil.com/mcb1700/picture.asp +# + +source [find target/lpc1768.cfg] + diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg new file mode 100644 index 00000000..59f11c5d --- /dev/null +++ b/tcl/target/lpc1768.cfg @@ -0,0 +1,49 @@ +# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc1768 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +#delays on reset lines +jtag_nsrst_delay 200 +jtag_ntrst_delay 200 + +# LPC2000 & LPC1700 -> SRST causes TRST +reset_config trst_and_srst srst_pulls_trst + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM) +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0 + +$_TARGETNAME configure -event reset-init { + soft_reset_halt + #do not remap 0x0000-0x0020 to anything but the flash +# mwb 0xE01FC040 0x01 + mwb 0xE000ED08 0x00 +} + +# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region). +# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum] + +flash bank lpc2000 0x0 0x80000 0 0 0 lpc1700 12000 calc_checksum + +# 4MHz / 6 = 666kHz, so use 500 +jtag_khz 500 |