Pieter Conradie <Pieter.Conradie@psitek.com> shuffle things around to the right spots. Should have been done in previous commit.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2604 b42882b7-edfa-0310-969c-e2dbd0fdcd60

4 files changed, 5 insertions, 129 deletions

diff --git a/tcl/board/at91sam9260.cfg b/tcl/board/at91sam9260.cfg
deleted file mode 100644
index 7f6d2eb8..00000000
--- a/tcl/board/at91sam9260.cfg
+++ /dev/null
@@ -1,44 +0,0 @@
-######################################
-# Target:    Atmel AT91SAM9260
-######################################
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME at91sam9260
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-   set  _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-  # force an error till we get a good number
-   set _CPUTAPID 0x0792603f
-}
-
-reset_config trst_and_srst separate trst_push_pull srst_open_drain
-
-#
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-jtag_nsrst_delay 300
-jtag_ntrst_delay 10
-
-jtag_rclk 3
-
-######################
-# Target configuration
-######################
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-
-# Internal sram1 memory
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
-
-
diff --git a/tcl/board/unknown-board-atmel-at91sam9260.cfg b/tcl/board/unknown-board-atmel-at91sam9260.cfg
deleted file mode 100644
index 4d69f0fd..00000000
--- a/tcl/board/unknown-board-atmel-at91sam9260.cfg
+++ /dev/null
@@ -1,82 +0,0 @@
-# Thanks to Pieter Conradie for this script! 
-# Target:    Atmel AT91SAM9260
-######################################
-
-# We add to the minimal configuration.
-source [find target/at91sam9260.cfg]
-
-######################
-# Target configuration
-######################
-
-$_TARGETNAME configure -event reset-init {
-	# at reset chip runs at 32khz
-	jtag_khz 8
-	mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
-	mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
-
-	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
-	sleep 20                          # wait 20 ms
-	mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
-	sleep 10                          # wait 10 ms
-	mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198,656MHz
-	sleep 20                          # wait 20 ms
-	mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler
-	sleep 10                          # wait 10 ms
-	mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected
-	sleep 10                          # wait 10 ms
-
-	# Now run at anything fast... ie: 10mhz!
-	jtag_khz 10000                    # Increase JTAG Speed to 6 MHz
-	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
-
-	mww 0xffffec00 0x01020102         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
-	mww 0xffffec04 0x09070806         # SMC_PULSE0
-	mww 0xffffec08 0x000d000b         # SMC_CYCLE0
-	mww 0xffffec0c 0x00001003         # SMC_MODE0
-
-	flash probe 0                     # Identify flash bank 0
-
-	mww 0xfffff870 0xffff0000         # PIO_ASR : Select peripheral function for D15..D31
-	mww 0xfffff804 0xffff0000         # PIO_PDR : Disable PIO function for D15..D31
-
-	mww 0xffffef1c 0x2                # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
-
-	#mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
-	mww 0xffffea08 0x85227254         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
-
-	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
-	mww 0x20000000 0
-	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
-	mww 0x20000000 0
-	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
-	mww 0x20000000 0
-	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
-	mww 0x20000000 0
-	mww 0xffffea04 0x5d2              # SDRAMC_TR : Set refresh timer count to 15us
-}
-
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 0
-
diff --git a/tcl/board/at91sam7sx.cfg b/tcl/target/at91sam7sx.cfg
index 516a09c7..516a09c7 100644
--- a/tcl/board/at91sam7sx.cfg
+++ b/tcl/target/at91sam7sx.cfg
diff --git a/tcl/target/at91sam9260.cfg b/tcl/target/at91sam9260.cfg
index 4d51831d..7f6d2eb8 100644
--- a/tcl/target/at91sam9260.cfg
+++ b/tcl/target/at91sam9260.cfg
@@ -21,13 +21,15 @@ if { [info exists CPUTAPID ] } {
    set _CPUTAPID 0x0792603f
 }
 
-reset_config trst_and_srst
+reset_config trst_and_srst separate trst_push_pull srst_open_drain
 
 #
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
+jtag_nsrst_delay 300
+jtag_ntrst_delay 10
+
+jtag_rclk 3
 
 ######################
 # Target configuration