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authordbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-25 17:02:59 +0000
committerdbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-25 17:02:59 +0000
commitad43374c7fe781ede0f5472f9cbdc55fc9486a6d (patch)
treebd4bc880e7f8ccd482ceb5a704d65e0fbfd32e4c /tcl
parent43b38078787fd4f0753bdc3b150300d34678618a (diff)
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Update DM355 target config to know about ICEpick.
Still defaults to nonstandard EMU0/EMU1 settings. git-svn-id: svn://svn.berlios.de/openocd/trunk@2757 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl')
-rw-r--r--tcl/target/ti_dm355.cfg23
1 files changed, 18 insertions, 5 deletions
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index abfba109..67b3f7a4 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -12,9 +12,16 @@ if { [info exists ENDIAN] } {
set _ENDIAN little
}
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+#set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
#
# Also note: when running without RTCK before the PLLs are set up, you
# may need to slow the JTAG clock down quite a lot (under 2 MHz).
@@ -26,7 +33,10 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
+jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
+ -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+ "icepick_c_tapenable $_CHIPNAME.jrc 1"
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID ] } {
@@ -34,7 +44,10 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x07926001
}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
+jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
+ -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+ "icepick_c_tapenable $_CHIPNAME.jrc 0"
# Primary TAP: ICEpick (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID ] } {