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authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-06-21 21:06:23 +0000
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-06-21 21:06:23 +0000
commitbc9df17e424887f37ae3d785c2e8faf4b70f0df2 (patch)
treec851756a610e10dd236b27697b5f981ebe954f71 /tcl
parentbed9c62f9ecf47e1633408efc31bd6c7aefe204b (diff)
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Paulius Zaleckas <paulius.zaleckas@gmail.com> Add config for CS351x CPUs
git-svn-id: svn://svn.berlios.de/openocd/trunk@2349 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl')
-rw-r--r--tcl/target/cs351x.cfg30
1 files changed, 30 insertions, 0 deletions
diff --git a/tcl/target/cs351x.cfg b/tcl/target/cs351x.cfg
new file mode 100644
index 00000000..51631d36
--- /dev/null
+++ b/tcl/target/cs351x.cfg
@@ -0,0 +1,30 @@
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME cs351x
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x00526fa1
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME -variant fa526
+# There is 16K of SRAM on this chip
+# FIXME: flash programming is not working by using this work area. So comment this out for now.
+#$_TARGETNAME configure -work-area-virt 0x00000000 -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1
+
+# This chip has a DCC ... use it
+arm7_9 dcc_downloads enable
+