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| author | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-23 22:03:41 +0000 |
|---|---|---|
| committer | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-23 22:03:41 +0000 |
| commit | 23e22b6ec42c137b48ef6359075a0fe819706f3c (patch) | |
| tree | 25dff748762ad388acb6e18c06907c0b09b792be /testing/examples/SAM7X256Test/test_ram.hex | |
| parent | 22045fa6f28813f9e7b17c052f4c7a6c8355178d (diff) | |
| download | openocd+libswd-23e22b6ec42c137b48ef6359075a0fe819706f3c.tar.gz openocd+libswd-23e22b6ec42c137b48ef6359075a0fe819706f3c.tar.bz2 openocd+libswd-23e22b6ec42c137b48ef6359075a0fe819706f3c.tar.xz openocd+libswd-23e22b6ec42c137b48ef6359075a0fe819706f3c.zip | |
Start handling the (second) SRST stage of reset better:
make sure that when there are two or more targets, their
various pre/post event reports are correctly ordered.
Previously, only the first target always saw its "pre"
method before SRST was asserted or deasserted.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2753 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'testing/examples/SAM7X256Test/test_ram.hex')
0 files changed, 0 insertions, 0 deletions