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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-18 15:04:58 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-18 15:04:58 -0800 |
| commit | f0c9e89e1a1747bf2bf40d42f3c7e795f73d41bb (patch) | |
| tree | b5589499f98ba5bb6bc484d1be661c1e90ad2c35 /testing/examples/STR912Test/test_rom.hex | |
| parent | 94dba423137d25fbe898fe7b04c451c6225a0079 (diff) | |
| download | openocd+libswd-f0c9e89e1a1747bf2bf40d42f3c7e795f73d41bb.tar.gz openocd+libswd-f0c9e89e1a1747bf2bf40d42f3c7e795f73d41bb.tar.bz2 openocd+libswd-f0c9e89e1a1747bf2bf40d42f3c7e795f73d41bb.tar.xz openocd+libswd-f0c9e89e1a1747bf2bf40d42f3c7e795f73d41bb.zip | |
Cortex-A8: xPSR handling updates
When we read the CPSR on debug entry, update the CPSR cache in all
cases, not just when the current processor state is User or System.
Plus minor cleanup of how the (too-many) other registers' cache
entries get updated.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'testing/examples/STR912Test/test_rom.hex')
0 files changed, 0 insertions, 0 deletions