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author | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-21 20:15:11 +0000 |
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committer | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-21 20:15:11 +0000 |
commit | 4da019edeb62154978dfac6a37e738814b2f2724 (patch) | |
tree | d77ed20c8d216292d902264ed16335ef071083ef /tools/rlink_make_speed_table | |
parent | eea0486263f173bc685cf0cfdda648ac5ab36c0a (diff) | |
download | openocd+libswd-4da019edeb62154978dfac6a37e738814b2f2724.tar.gz openocd+libswd-4da019edeb62154978dfac6a37e738814b2f2724.tar.bz2 openocd+libswd-4da019edeb62154978dfac6a37e738814b2f2724.tar.xz openocd+libswd-4da019edeb62154978dfac6a37e738814b2f2724.zip |
David Brownell <david-b@pacbell.net>:
Clean up treatment of registers in ARMv7-M and Cortex-M3.
- At the arch level:
* Just list registers and names; don't impose core-specific
policy about how they are accessed.
* Each register has a symbol.
* Remove the register mode field (irrelevant to debugger)
- At the core/implementation level:
* Just map the registers to their relevant access methods;
don't require the arch level to say how that should work
(cores other than Cortex-M3 could do it differently).
* Don't use undefined bits from register 20.
* Use register IDs that are part of the ARMv7-M interface.
In short, there's now a real distinction between the arch
and core layers.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tools/rlink_make_speed_table')
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