diff options
| -rw-r--r-- | src/target/event/xba_revA3.script | 40 | ||||
| -rw-r--r-- | src/target/target/xba_revA3.cfg | 28 |
2 files changed, 68 insertions, 0 deletions
diff --git a/src/target/event/xba_revA3.script b/src/target/event/xba_revA3.script new file mode 100644 index 00000000..b58c7a23 --- /dev/null +++ b/src/target/event/xba_revA3.script @@ -0,0 +1,40 @@ +#Written by: Michael Schwingen <rincewind@discworld.dascon.de>
+#############################################################################
+# setup expansion bus CS, disable external wdt
+#############################################################################
+mww 0xc4000000 0xbd113842 #CS0 : Flash, write enabled @0x50000000
+mww 0xc4000004 0x94d10013 #CS1
+mww 0xc4000008 0x95960003 #CS2
+mww 0xc400000c 0x00000000 #CS3
+mww 0xc4000010 0x80900003 #CS4
+mww 0xc4000014 0x9d520003 #CS5
+mww 0xc4000018 0x81860001 #CS6
+mww 0xc400001c 0x80900003 #CS7
+
+#############################################################################
+# init SDRAM controller: 16MB, one bank, CL3
+#############################################################################
+mww 0xCC000000 0x2A # SDRAM_CFG: 64MBit, CL3
+mww 0xCC000004 0 # disable refresh
+mww 0xCC000008 3 # NOP
+sleep 100
+mww 0xCC000004 2100 # set refresh counter
+mww 0xCC000008 2 # Precharge All Banks
+sleep 100
+mww 0xCC000008 4 # Auto Refresh
+mww 0xCC000008 4 # Auto Refresh
+mww 0xCC000008 4 # Auto Refresh
+mww 0xCC000008 4 # Auto Refresh
+mww 0xCC000008 4 # Auto Refresh
+mww 0xCC000008 4 # Auto Refresh
+mww 0xCC000008 4 # Auto Refresh
+mww 0xCC000008 4 # Auto Refresh
+mww 0xCC000008 1 # Mode Select CL3
+
+#mww 0xc4000020 0xffffee # CFG0: remove expansion bus boot flash
+#mirror at 0x00000000
+
+#
+# detect flash
+#
+flash probe 0
diff --git a/src/target/target/xba_revA3.cfg b/src/target/target/xba_revA3.cfg new file mode 100644 index 00000000..2fb83721 --- /dev/null +++ b/src/target/target/xba_revA3.cfg @@ -0,0 +1,28 @@ +#Written by: Michael Schwingen <rincewind@discworld.dascon.de>
+
+reset_config trst_and_srst separate
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR capture Mask, IDCODE)
+jtag_device 7 0x1 0x7f 0x7e
+
+daemon_startup reset
+
+#target <type> <endianess> <reset mode> <JTAG pos> <variant>
+target xscale big reset_init 0 ixp42x
+#target xscale big run_and_halt 0 ixp42x
+target_script 0 reset event/xba_revA3.script
+
+run_and_halt_time 0 100
+
+flash bank cfi 0x50000000 0x400000 2 2 0
+working_area 0 0x20010000 0x8000 nobackup
+
+# halt target
+wait_halt
+
+# set big endian mode
+reg XSCALE_CTRL 0xF8
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