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-rw-r--r--src/target/arm11.c2
-rw-r--r--src/target/arm7_9_common.c23
-rw-r--r--src/target/arm920t.c8
-rw-r--r--src/target/armv4_5.c35
-rw-r--r--src/target/armv4_5.h6
-rw-r--r--src/target/xscale.c5
6 files changed, 39 insertions, 40 deletions
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 5e732758..3a235852 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1603,7 +1603,7 @@ static int arm11_run_algorithm(struct target *target,
}
// FIXME
-// if (armv4_5_mode_to_number(arm11->core_mode)==-1)
+// if (!is_arm_mode(arm11->core_mode))
// return ERROR_FAIL;
// Save regs
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index ff95a0cd..37aa0660 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1242,9 +1242,6 @@ int arm7_9_soft_reset_halt(struct target *target)
armv4_5->core_mode = ARMV4_5_MODE_SVC;
armv4_5->core_state = ARMV4_5_STATE_ARM;
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
- return ERROR_FAIL;
-
/* reset registers */
for (i = 0; i <= 14; i++)
{
@@ -1413,7 +1410,7 @@ static int arm7_9_debug_entry(struct target *target)
armv4_5->core_mode = cpsr & 0x1f;
- if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
+ if (!is_arm_mode(armv4_5->core_mode))
{
target->state = TARGET_UNKNOWN;
LOG_ERROR("cpsr contains invalid mode value - communication failure");
@@ -1439,9 +1436,6 @@ static int arm7_9_debug_entry(struct target *target)
else
context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
- return ERROR_FAIL;
-
for (i = 0; i <= 15; i++)
{
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
@@ -1452,9 +1446,6 @@ static int arm7_9_debug_entry(struct target *target)
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
- return ERROR_FAIL;
-
/* exceptions other than USR & SYS have a saved program status register */
if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
{
@@ -1506,7 +1497,7 @@ int arm7_9_full_context(struct target *target)
return ERROR_TARGET_NOT_HALTED;
}
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
@@ -1606,7 +1597,7 @@ int arm7_9_restore_context(struct target *target)
if (arm7_9->pre_restore_context)
arm7_9->pre_restore_context(target);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
@@ -2104,7 +2095,7 @@ int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
@@ -2168,7 +2159,7 @@ int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
@@ -2373,7 +2364,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
break;
}
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
for (i = 0; i <= last_reg; i++)
@@ -2556,7 +2547,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
embeddedice_store_reg(dbg_ctrl);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
for (i = 0; i <= last_reg; i++)
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index e1dcea7a..29f7917d 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -244,7 +244,7 @@ static int arm920t_read_cp15_interpreted(struct target *target,
LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
#endif
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
@@ -284,7 +284,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
#endif
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
@@ -889,7 +889,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
fclose(output);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* mark registers dirty. */
@@ -1172,7 +1172,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
fclose(output);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* mark registers dirty */
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 6864efbb..d22e0f3a 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -36,7 +36,7 @@
#include "register.h"
-char* armv4_5_core_reg_list[] =
+static const char *armv4_5_core_reg_list[] =
{
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
@@ -101,9 +101,7 @@ static const struct {
/** Map PSR mode bits to the name of an ARM processor operating mode. */
const char *arm_mode_name(unsigned psr_mode)
{
- unsigned i;
-
- for (i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
+ for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
if (arm_mode_data[i].psr == psr_mode)
return arm_mode_data[i].name;
}
@@ -111,7 +109,17 @@ const char *arm_mode_name(unsigned psr_mode)
return "UNRECOGNIZED";
}
-/** Map PSR mode bits to linear number */
+/** Return true iff the parameter denotes a valid ARM processor mode. */
+bool is_arm_mode(unsigned psr_mode)
+{
+ for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
+ if (arm_mode_data[i].psr == psr_mode)
+ return true;
+ }
+ return false;
+}
+
+/** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
int armv4_5_mode_to_number(enum armv4_5_mode mode)
{
switch (mode) {
@@ -137,7 +145,7 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode)
}
}
-/** Map linear number to PSR mode bits. */
+/** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
enum armv4_5_mode armv4_5_number_to_mode(int number)
{
switch (number) {
@@ -166,7 +174,7 @@ char* armv4_5_state_strings[] =
"ARM", "Thumb", "Jazelle"
};
-struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
+static const struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
{
{0, ARMV4_5_MODE_ANY, NULL, NULL},
{1, ARMV4_5_MODE_ANY, NULL, NULL},
@@ -214,7 +222,7 @@ struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
};
/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
-int armv4_5_core_reg_map[7][17] =
+const int armv4_5_core_reg_map[7][17] =
{
{ /* USR */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
@@ -383,7 +391,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
arch_info[i] = armv4_5_core_reg_list_arch_info[i];
arch_info[i].target = target;
arch_info[i].armv4_5_common = armv4_5_common;
- reg_list[i].name = armv4_5_core_reg_list[i];
+ reg_list[i].name = (char *) armv4_5_core_reg_list[i];
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0;
@@ -415,6 +423,9 @@ int armv4_5_arch_state(struct target *target)
return ERROR_OK;
}
+#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
+ cache->reg_list[armv4_5_core_reg_map[mode][num]]
+
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
char output[128];
@@ -435,7 +446,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
return ERROR_OK;
}
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
if (!armv4_5->full_context) {
@@ -599,7 +610,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int i;
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
*reg_list_size = 26;
@@ -679,7 +690,7 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
return ERROR_TARGET_NOT_HALTED;
}
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* armv5 and later can terminate with BKPT instruction; less overhead */
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 5b7a5220..81eac476 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -42,6 +42,8 @@ typedef enum armv4_5_mode
} armv4_5_mode_t;
const char *arm_mode_name(unsigned psr_mode);
+bool is_arm_mode(unsigned psr_mode);
+
int armv4_5_mode_to_number(enum armv4_5_mode mode);
enum armv4_5_mode armv4_5_number_to_mode(int number);
@@ -54,12 +56,10 @@ typedef enum armv4_5_state
extern char* armv4_5_state_strings[];
-extern int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[7][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
-#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
- cache->reg_list[armv4_5_core_reg_map[mode][num]]
/* offsets into armv4_5 core register cache */
enum
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 38928f41..09e68254 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -954,7 +954,7 @@ static int xscale_debug_entry(struct target *target)
LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
armv4_5->core_mode = buffer[9] & 0x1f;
- if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
+ if (!is_arm_mode(armv4_5->core_mode))
{
target->state = TARGET_UNKNOWN;
LOG_ERROR("cpsr contains invalid mode value - communication failure");
@@ -969,9 +969,6 @@ static int xscale_debug_entry(struct target *target)
armv4_5->core_state = ARMV4_5_STATE_ARM;
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
- return ERROR_FAIL;
-
/* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
{
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-26 02:01:18 +0000