diff options
| -rw-r--r-- | src/flash/nor/lpc2000.c | 7 | ||||
| -rw-r--r-- | src/target/arm11.c | 1 | ||||
| -rw-r--r-- | src/target/arm720t.c | 1 | ||||
| -rw-r--r-- | src/target/arm7tdmi.c | 1 | ||||
| -rw-r--r-- | src/target/arm920t.c | 1 | ||||
| -rw-r--r-- | src/target/arm926ejs.c | 1 | ||||
| -rw-r--r-- | src/target/arm966e.c | 1 | ||||
| -rw-r--r-- | src/target/arm9tdmi.c | 1 | ||||
| -rw-r--r-- | src/target/arm_dpm.c | 1 | ||||
| -rw-r--r-- | src/target/arm_opcodes.h | 260 | ||||
| -rw-r--r-- | src/target/armv4_5.h | 167 | ||||
| -rw-r--r-- | src/target/armv7a.c | 2 | ||||
| -rw-r--r-- | src/target/armv7m.h | 79 | ||||
| -rw-r--r-- | src/target/cortex_a8.c | 1 | ||||
| -rw-r--r-- | src/target/cortex_m3.c | 3 | ||||
| -rw-r--r-- | src/target/fa526.c | 1 | ||||
| -rw-r--r-- | src/target/feroceon.c | 1 | ||||
| -rw-r--r-- | src/target/xscale.c | 1 |
18 files changed, 281 insertions, 249 deletions
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c index 0caf3e09..18896f7b 100644 --- a/src/flash/nor/lpc2000.c +++ b/src/flash/nor/lpc2000.c @@ -29,6 +29,7 @@ #include "lpc2000.h" #include <helper/binarybuffer.h> #include <target/algorithm.h> +#include <target/arm_opcodes.h> #include <target/armv7m.h> @@ -263,8 +264,10 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta switch(lpc2000_info->variant) { case lpc1700: - target_buffer_set_u32(target, jump_gate, ARMV7M_T_BX(12)); - target_buffer_set_u32(target, jump_gate + 4, ARMV7M_T_B(0xfffffe)); + target_buffer_set_u32(target, jump_gate, + ARMV4_5_T_BX(12)); + target_buffer_set_u32(target, jump_gate + 4, + ARMV4_5_T_B(0xfffffe)); break; case lpc2000_v1: case lpc2000_v2: diff --git a/src/target/arm11.c b/src/target/arm11.c index 0486b04c..7868c23b 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -34,6 +34,7 @@ #include "target_type.h" #include "algorithm.h" #include "register.h" +#include "arm_opcodes.h" #if 0 diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 207db787..14d21849 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -28,6 +28,7 @@ #include <helper/time_support.h> #include "target_type.h" #include "register.h" +#include "arm_opcodes.h" /* diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index fffc6327..d204f95e 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -30,6 +30,7 @@ #include "arm7tdmi.h" #include "target_type.h" #include "register.h" +#include "arm_opcodes.h" /* diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 6a005d6d..1fcae435 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -25,6 +25,7 @@ #include <helper/time_support.h> #include "target_type.h" #include "register.h" +#include "arm_opcodes.h" /* diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index cacb9428..d882050f 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -28,6 +28,7 @@ #include <helper/time_support.h> #include "target_type.h" #include "register.h" +#include "arm_opcodes.h" /* diff --git a/src/target/arm966e.c b/src/target/arm966e.c index 9fe513c9..e4bfe573 100644 --- a/src/target/arm966e.c +++ b/src/target/arm966e.c @@ -26,6 +26,7 @@ #include "arm966e.h" #include "target_type.h" +#include "arm_opcodes.h" #if 0 diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 09199c70..05f02464 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -30,6 +30,7 @@ #include "arm9tdmi.h" #include "target_type.h" #include "register.h" +#include "arm_opcodes.h" /* diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 1ddf530c..406e30a2 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -27,6 +27,7 @@ #include "register.h" #include "breakpoints.h" #include "target_type.h" +#include "arm_opcodes.h" /** diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h new file mode 100644 index 00000000..b3b51433 --- /dev/null +++ b/src/target/arm_opcodes.h @@ -0,0 +1,260 @@ +/* + * Copyright (C) 2005 by Dominic Rath + * Dominic.Rath@gmx.de + * + * Copyright (C) 2008 by Spencer Oliver + * spen@spen-soft.co.uk + * + * Copyright (C) 2009 by Øyvind Harboe + * oyvind.harboe@zylin.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the + * Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#ifndef __ARM_OPCODES_H +#define __ARM_OPCODES_H + +/* ARM mode instructions */ + +/* Store multiple increment after + * Rn: base register + * List: for each bit in list: store register + * S: in priviledged mode: store user-mode registers + * W = 1: update the base register. W = 0: leave the base register untouched + */ +#define ARMV4_5_STMIA(Rn, List, S, W) \ + (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) + +/* Load multiple increment after + * Rn: base register + * List: for each bit in list: store register + * S: in priviledged mode: store user-mode registers + * W = 1: update the base register. W = 0: leave the base register untouched + */ +#define ARMV4_5_LDMIA(Rn, List, S, W) \ + (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) + +/* MOV r8, r8 */ +#define ARMV4_5_NOP (0xe1a08008) + +/* Move PSR to general purpose register + * R = 1: SPSR R = 0: CPSR + * Rn: target register + */ +#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12)) + +/* Store register + * Rd: register to store + * Rn: base register + */ +#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16)) + +/* Load register + * Rd: register to load + * Rn: base register + */ +#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16)) + +/* Move general purpose register to PSR + * R = 1: SPSR R = 0: CPSR + * Field: Field mask + * 1: control field 2: extension field 4: status field 8: flags field + * Rm: source register + */ +#define ARMV4_5_MSR_GP(Rm, Field, R) \ + (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22)) +#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \ + (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22)) + +/* Load Register Halfword Immediate Post-Index + * Rd: register to load + * Rn: base register + */ +#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16)) + +/* Load Register Byte Immediate Post-Index + * Rd: register to load + * Rn: base register + */ +#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16)) + +/* Store register Halfword Immediate Post-Index + * Rd: register to store + * Rn: base register + */ +#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16)) + +/* Store register Byte Immediate Post-Index + * Rd: register to store + * Rn: base register + */ +#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16)) + +/* Branch (and Link) + * Im: Branch target (left-shifted by 2 bits, added to PC) + * L: 1: branch and link 0: branch only + */ +#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24)) + +/* Branch and exchange (ARM state) + * Rm: register holding branch target address + */ +#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm)) + +/* Move to ARM register from coprocessor + * CP: Coprocessor number + * op1: Coprocessor opcode + * Rd: destination register + * CRn: first coprocessor operand + * CRm: second coprocessor operand + * op2: Second coprocessor opcode + */ +#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \ + (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \ + | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) + +/* Move to coprocessor from ARM register + * CP: Coprocessor number + * op1: Coprocessor opcode + * Rd: destination register + * CRn: first coprocessor operand + * CRm: second coprocessor operand + * op2: Second coprocessor opcode + */ +#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \ + (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \ + | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) + +/* Breakpoint instruction (ARMv5) + * Im: 16-bit immediate + */ +#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf)) + + +/* Thumb mode instructions + * + * FIXME there must be some reason all these opcodes are 32-bits + * not 16-bits ... this should get either an explanatory comment, + * or be changed not to duplicate the opcode. + */ + +/* Store register (Thumb mode) + * Rd: source register + * Rn: base register + */ +#define ARMV4_5_T_STR(Rd, Rn) \ + ((0x6000 | (Rd) | ((Rn) << 3)) | \ + ((0x6000 | (Rd) | ((Rn) << 3)) << 16)) + +/* Load register (Thumb state) + * Rd: destination register + * Rn: base register + */ +#define ARMV4_5_T_LDR(Rd, Rn) \ + ((0x6800 | ((Rn) << 3) | (Rd)) \ + | ((0x6800 | ((Rn) << 3) | (Rd)) << 16)) + +/* Load multiple (Thumb state) + * Rn: base register + * List: for each bit in list: store register + */ +#define ARMV4_5_T_LDMIA(Rn, List) \ + ((0xc800 | ((Rn) << 8) | (List)) \ + | ((0xc800 | ((Rn) << 8) | (List)) << 16)) + +/* Load register with PC relative addressing + * Rd: register to load + */ +#define ARMV4_5_T_LDR_PCREL(Rd) \ + ((0x4800 | ((Rd) << 8)) \ + | ((0x4800 | ((Rd) << 8)) << 16)) + +/* Move hi register (Thumb mode) + * Rd: destination register + * Rm: source register + */ +#define ARMV4_5_T_MOV(Rd, Rm) \ + ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \ + (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \ + | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \ + (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16)) + +/* No operation (Thumb mode) + * NOTE: this is "MOV r8, r8" ... Thumb2 adds two + * architected NOPs, 16-bit and 32-bit. + */ +#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16)) + +/* Move immediate to register (Thumb state) + * Rd: destination register + * Im: 8-bit immediate value + */ +#define ARMV4_5_T_MOV_IM(Rd, Im) \ + ((0x2000 | ((Rd) << 8) | (Im)) \ + | ((0x2000 | ((Rd) << 8) | (Im)) << 16)) + +/* Branch and Exchange + * Rm: register containing branch target + */ +#define ARMV4_5_T_BX(Rm) \ + ((0x4700 | ((Rm) << 3)) \ + | ((0x4700 | ((Rm) << 3)) << 16)) + +/* Branch (Thumb state) + * Imm: Branch target + */ +#define ARMV4_5_T_B(Imm) \ + ((0xe000 | (Imm)) \ + | ((0xe000 | (Imm)) << 16)) + +/* Breakpoint instruction (ARMv5) (Thumb state) + * Im: 8-bit immediate + */ +#define ARMV5_T_BKPT(Im) \ + ((0xbe00 | (Im)) \ + | ((0xbe00 | (Im)) << 16)) + +/* Move to Register from Special Register + * 32 bit Thumb2 instruction + * Rd: destination register + * SYSm: source special register + */ +#define ARM_T2_MRS(Rd, SYSm) \ + ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) + +/* Move from Register from Special Register + * 32 bit Thumb2 instruction + * Rd: source register + * SYSm: destination special register + */ +#define ARM_T2_MSR(SYSm, Rn) \ + ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16)) + +/* Change Processor State. + * 16 bit Thumb2 instruction + * Rd: source register + * IF: A_FLAG and/or I_FLAG and/or F_FLAG + */ +#define A_FLAG 4 +#define I_FLAG 2 +#define F_FLAG 1 +#define ARM_T2_CPSID(IF) \ + ((0xB660 | (1 << 8) | ((IF)&0x3)) \ + | ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16)) +#define ARM_T2_CPSIE(IF) \ + ((0xB660 | (0 << 8) | ((IF)&0x3)) \ + | ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16)) + +#endif /* __ARM_OPCODES_H */ diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index 6e289337..4b2ccf82 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -212,171 +212,4 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum); extern struct reg arm_gdb_dummy_fp_reg; extern struct reg arm_gdb_dummy_fps_reg; -/* ARM mode instructions - */ - -/* Store multiple increment after - * Rn: base register - * List: for each bit in list: store register - * S: in priviledged mode: store user-mode registers - * W = 1: update the base register. W = 0: leave the base register untouched - */ -#define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) - -/* Load multiple increment after - * Rn: base register - * List: for each bit in list: store register - * S: in priviledged mode: store user-mode registers - * W = 1: update the base register. W = 0: leave the base register untouched - */ -#define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) - -/* MOV r8, r8 */ -#define ARMV4_5_NOP (0xe1a08008) - -/* Move PSR to general purpose register - * R = 1: SPSR R = 0: CPSR - * Rn: target register - */ -#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12)) - -/* Store register - * Rd: register to store - * Rn: base register - */ -#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16)) - -/* Load register - * Rd: register to load - * Rn: base register - */ -#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16)) - -/* Move general purpose register to PSR - * R = 1: SPSR R = 0: CPSR - * Field: Field mask - * 1: control field 2: extension field 4: status field 8: flags field - * Rm: source register - */ -#define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22)) -#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22)) - -/* Load Register Halfword Immediate Post-Index - * Rd: register to load - * Rn: base register - */ -#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16)) - -/* Load Register Byte Immediate Post-Index - * Rd: register to load - * Rn: base register - */ -#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16)) - -/* Store register Halfword Immediate Post-Index - * Rd: register to store - * Rn: base register - */ -#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16)) - -/* Store register Byte Immediate Post-Index - * Rd: register to store - * Rn: base register - */ -#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16)) - -/* Branch (and Link) - * Im: Branch target (left-shifted by 2 bits, added to PC) - * L: 1: branch and link 0: branch only - */ -#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24)) - -/* Branch and exchange (ARM state) - * Rm: register holding branch target address - */ -#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm)) - -/* Move to ARM register from coprocessor - * CP: Coprocessor number - * op1: Coprocessor opcode - * Rd: destination register - * CRn: first coprocessor operand - * CRm: second coprocessor operand - * op2: Second coprocessor opcode - */ -#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) - -/* Move to coprocessor from ARM register - * CP: Coprocessor number - * op1: Coprocessor opcode - * Rd: destination register - * CRn: first coprocessor operand - * CRm: second coprocessor operand - * op2: Second coprocessor opcode - */ -#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) - -/* Breakpoint instruction (ARMv5) - * Im: 16-bit immediate - */ -#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf)) - - -/* Thumb mode instructions - */ - -/* Store register (Thumb mode) - * Rd: source register - * Rn: base register - */ -#define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16)) - -/* Load register (Thumb state) - * Rd: destination register - * Rn: base register - */ -#define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16)) - -/* Load multiple (Thumb state) - * Rn: base register - * List: for each bit in list: store register - */ -#define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16)) - -/* Load register with PC relative addressing - * Rd: register to load - */ -#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16)) - -/* Move hi register (Thumb mode) - * Rd: destination register - * Rm: source register - */ -#define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16)) - -/* No operation (Thumb mode) - */ -#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16)) - -/* Move immediate to register (Thumb state) - * Rd: destination register - * Im: 8-bit immediate value - */ -#define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16)) - -/* Branch and Exchange - * Rm: register containing branch target - */ -#define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16)) - -/* Branch (Thumb state) - * Imm: Branch target - */ -#define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16)) - -/* Breakpoint instruction (ARMv5) (Thumb state) - * Im: 8-bit immediate - */ -#define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16)) - #endif /* ARMV4_5_H */ diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 300ac283..3cc86bc6 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -33,6 +33,8 @@ #include <string.h> #include <unistd.h> +#include "arm_opcodes.h" + static void armv7a_show_fault_registers(struct target *target) { diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 353860a9..c60ab8cf 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -162,83 +162,4 @@ int armv7m_blank_check_memory(struct target *target, extern const struct command_registration armv7m_command_handlers[]; -/* Thumb mode instructions - */ - -/* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction - * Rd: destination register - * SYSm: source special register - */ -#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) - -/* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction - * Rd: source register - * SYSm: destination special register - */ -#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16)) - -/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK - * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction - * Rd: source register - * IF: - */ -#define I_FLAG 2 -#define F_FLAG 1 -#define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16)) -#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16)) - -/* Breakpoint (Thumb mode) v5 onwards - * Im: immediate value used by debugger - */ -#define ARMV7M_T_BKPT(Im) ((0xBE00 | Im) | ((0xBE00 | Im) << 16)) - -/* Store register (Thumb mode) - * Rd: source register - * Rn: base register - */ -#define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16)) - -/* Load register (Thumb state) - * Rd: destination register - * Rn: base register - */ -#define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16)) - -/* Load multiple (Thumb state) - * Rn: base register - * List: for each bit in list: store register - */ -#define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16)) - -/* Load register with PC relative addressing - * Rd: register to load - */ -#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16)) - -/* Move hi register (Thumb mode) - * Rd: destination register - * Rm: source register - */ -#define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16)) - -/* No operation (Thumb mode) - */ -#define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16)) - -/* Move immediate to register (Thumb state) - * Rd: destination register - * Im: 8-bit immediate value - */ -#define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16)) - -/* Branch and Exchange - * Rm: register containing branch target - */ -#define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16)) - -/* Branch (Thumb state) - * Imm: Branch target - */ -#define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16)) - #endif /* ARMV7M_H */ diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 57e4bcdf..1ac0a303 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -38,6 +38,7 @@ #include "register.h" #include "target_request.h" #include "target_type.h" +#include "arm_opcodes.h" static int cortex_a8_poll(struct target *target); static int cortex_a8_debug_entry(struct target *target); diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 195a3b9a..558b2117 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -37,6 +37,7 @@ #include "target_type.h" #include "arm_disassembler.h" #include "register.h" +#include "arm_opcodes.h" /* NOTE: most of this should work fine for the Cortex-M1 and @@ -880,7 +881,7 @@ cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint) else if (breakpoint->type == BKPT_SOFT) { uint8_t code[4]; - buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11)); + buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11)); if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; diff --git a/src/target/fa526.c b/src/target/fa526.c index 32469d0d..9c01ec7f 100644 --- a/src/target/fa526.c +++ b/src/target/fa526.c @@ -33,6 +33,7 @@ #include "arm920t.h" #include "target_type.h" +#include "arm_opcodes.h" static void fa526_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc) { diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 1c701540..c9121376 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -56,6 +56,7 @@ #include "arm966e.h" #include "target_type.h" #include "register.h" +#include "arm_opcodes.h" int feroceon_assert_reset(struct target *target) diff --git a/src/target/xscale.c b/src/target/xscale.c index d5b1d636..b36d9fdc 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -36,6 +36,7 @@ #include <helper/time_support.h> #include "register.h" #include "image.h" +#include "arm_opcodes.h" /* |