diff options
| -rw-r--r-- | src/flash/lpc3180_nand_controller.c | 260 | ||||
| -rw-r--r-- | src/flash/nand.c | 320 | ||||
| -rw-r--r-- | src/flash/nand.h | 28 | ||||
| -rw-r--r-- | src/flash/s3c2410_nand.c | 18 | ||||
| -rw-r--r-- | src/flash/s3c2412_nand.c | 2 | ||||
| -rw-r--r-- | src/flash/s3c2440_nand.c | 14 | ||||
| -rw-r--r-- | src/flash/s3c2443_nand.c | 4 | ||||
| -rw-r--r-- | src/flash/s3c24xx_nand.c | 16 | ||||
| -rw-r--r-- | src/flash/s3c24xx_nand.h | 4 | ||||
| -rw-r--r-- | src/flash/stellaris.h | 5 | ||||
| -rw-r--r-- | src/flash/stm32x.h | 6 | ||||
| -rw-r--r-- | src/flash/str7x.h | 8 |
12 files changed, 342 insertions, 343 deletions
diff --git a/src/flash/lpc3180_nand_controller.c b/src/flash/lpc3180_nand_controller.c index ffe7ce2b..50846b92 100644 --- a/src/flash/lpc3180_nand_controller.c +++ b/src/flash/lpc3180_nand_controller.c @@ -61,13 +61,13 @@ nand_flash_controller_t lpc3180_nand_controller = static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device) { lpc3180_nand_controller_t *lpc3180_info; - + if (argc < 3) { LOG_WARNING("incomplete 'lpc3180' nand flash configuration"); return ERROR_FLASH_BANK_INVALID; } - + lpc3180_info = malloc(sizeof(lpc3180_nand_controller_t)); device->controller_priv = lpc3180_info; @@ -81,22 +81,22 @@ static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char * lpc3180_info->osc_freq = strtoul(args[2], NULL, 0); if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000)) { - LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq); + LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq); } lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER; lpc3180_info->sw_write_protection = 0; lpc3180_info->sw_wp_lower_bound = 0x0; lpc3180_info->sw_wp_upper_bound = 0x0; - + return ERROR_OK; } static int lpc3180_register_commands(struct command_context_s *cmd_ctx) { command_t *lpc3180_cmd = register_command(cmd_ctx, NULL, "lpc3180", NULL, COMMAND_ANY, "commands specific to the LPC3180 NAND flash controllers"); - + register_command(cmd_ctx, lpc3180_cmd, "select", handle_lpc3180_select_command, COMMAND_EXEC, "select <'mlc'|'slc'> controller (default is mlc)"); - + return ERROR_OK; } @@ -112,20 +112,20 @@ static int lpc3180_pll(int fclkin, u32 pll_ctrl) if (!lock) LOG_WARNING("PLL is not locked"); - + if (!bypass && direct) /* direct mode */ return (m * fclkin) / n; - + if (bypass && !direct) /* bypass mode */ return fclkin / (2 * p); - + if (bypass & direct) /* direct bypass mode */ return fclkin; - + if (feedback) /* integer mode */ return m * (fclkin / n); else /* non-integer mode */ - return (m / (2 * p)) * (fclkin / n); + return (m / (2 * p)) * (fclkin / n); } static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info) @@ -136,20 +136,20 @@ static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info) int hclk; int hclk_pll; float cycle; - + /* calculate timings */ - - /* determine current SYSCLK (13'MHz or main oscillator) */ + + /* determine current SYSCLK (13'MHz or main oscillator) */ target_read_u32(target, 0x40004050, &sysclk_ctrl); - + if ((sysclk_ctrl & 1) == 0) sysclk = lpc3180_info->osc_freq; else sysclk = 13000; - + /* determine selected HCLK source */ target_read_u32(target, 0x40004044, &pwr_ctrl); - + if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */ { hclk = sysclk; @@ -160,21 +160,21 @@ static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info) hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl); target_read_u32(target, 0x40004040, &hclkdiv_ctrl); - + if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */ { hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1); } else /* HCLK uses HCLK_PLL */ { - hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3)); + hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3)); } } - + LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk); - + cycle = (1.0 / hclk) * 1000000.0; - + return cycle; } @@ -185,20 +185,20 @@ static int lpc3180_init(struct nand_device_s *device) int bus_width = (device->bus_width) ? (device->bus_width) : 8; int address_cycles = (device->address_cycles) ? (device->address_cycles) : 3; int page_size = (device->page_size) ? (device->page_size) : 512; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + /* sanitize arguments */ if ((bus_width != 8) && (bus_width != 16)) { LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width); return ERROR_NAND_OPERATION_NOT_SUPPORTED; } - + /* The LPC3180 only brings out 8 bit NAND data bus, but the controller * would support 16 bit, too, so we just warn about this for now */ @@ -206,44 +206,44 @@ static int lpc3180_init(struct nand_device_s *device) { LOG_WARNING("LPC3180 only supports 8 bit bus width"); } - + /* inform calling code about selected bus width */ device->bus_width = bus_width; - + if ((address_cycles != 3) && (address_cycles != 4)) { LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles); return ERROR_NAND_OPERATION_NOT_SUPPORTED; } - + if ((page_size != 512) && (page_size != 2048)) { LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size); return ERROR_NAND_OPERATION_NOT_SUPPORTED; } - + /* select MLC controller if none is currently selected */ if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) { LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'"); lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER; } - + if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) { u32 mlc_icr_value = 0x0; float cycle; int twp, twh, trp, treh, trhz, trbwb, tcea; - + /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */ target_write_u32(target, 0x400040c8, 0x22); - + /* MLC_CEH = 0x0 (Force nCE assert) */ target_write_u32(target, 0x200b804c, 0x0); - + /* MLC_LOCK = 0xa25e (unlock protected registers) */ target_write_u32(target, 0x200b8044, 0xa25e); - + /* MLC_ICR = configuration */ if (lpc3180_info->sw_write_protection) mlc_icr_value |= 0x8; @@ -254,10 +254,10 @@ static int lpc3180_init(struct nand_device_s *device) if (bus_width == 16) mlc_icr_value |= 0x1; target_write_u32(target, 0x200b8030, mlc_icr_value); - + /* calculate NAND controller timings */ cycle = lpc3180_cycle_time(lpc3180_info); - + twp = ((40 / cycle) + 1); twh = ((20 / cycle) + 1); trp = ((30 / cycle) + 1); @@ -265,14 +265,14 @@ static int lpc3180_init(struct nand_device_s *device) trhz = ((30 / cycle) + 1); trbwb = ((100 / cycle) + 1); tcea = ((45 / cycle) + 1); - + /* MLC_LOCK = 0xa25e (unlock protected registers) */ target_write_u32(target, 0x200b8044, 0xa25e); - + /* MLC_TIME_REG */ - target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) | - ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) | - ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24)); + target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) | + ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) | + ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24)); lpc3180_reset(device); } @@ -281,30 +281,30 @@ static int lpc3180_init(struct nand_device_s *device) float cycle; int r_setup, r_hold, r_width, r_rdy; int w_setup, w_hold, w_width, w_rdy; - + /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */ target_write_u32(target, 0x400040c8, 0x05); - + /* SLC_CFG = 0x (Force nCE assert, ECC enabled, WIDTH = bus_width) */ target_write_u32(target, 0x20020014, 0x28 | (bus_width == 16) ? 1 : 0); - + /* calculate NAND controller timings */ cycle = lpc3180_cycle_time(lpc3180_info); - + r_setup = w_setup = 0; r_hold = w_hold = 10 / cycle; r_width = 30 / cycle; w_width = 40 / cycle; r_rdy = w_rdy = 100 / cycle; - + /* SLC_TAC: SLC timing arcs register */ target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) | ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) | ((w_setup & 0xf) << 16) | - ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28)); - + ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28)); + lpc3180_reset(device); } - + return ERROR_OK; } @@ -312,13 +312,13 @@ static int lpc3180_reset(struct nand_device_s *device) { lpc3180_nand_controller_t *lpc3180_info = device->controller_priv; target_t *target = lpc3180_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) { LOG_ERROR("BUG: no LPC3180 NAND flash controller selected"); @@ -339,14 +339,14 @@ static int lpc3180_reset(struct nand_device_s *device) { /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */ target_write_u32(target, 0x20020010, 0x6); - + if (!lpc3180_controller_ready(device, 100)) { LOG_ERROR("LPC3180 NAND controller timed out after reset"); return ERROR_NAND_OPERATION_TIMEOUT; } } - + return ERROR_OK; } @@ -354,13 +354,13 @@ static int lpc3180_command(struct nand_device_s *device, u8 command) { lpc3180_nand_controller_t *lpc3180_info = device->controller_priv; target_t *target = lpc3180_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) { LOG_ERROR("BUG: no LPC3180 NAND flash controller selected"); @@ -375,8 +375,8 @@ static int lpc3180_command(struct nand_device_s *device, u8 command) { /* SLC_CMD = command */ target_write_u32(target, 0x20020008, command); - } - + } + return ERROR_OK; } @@ -384,13 +384,13 @@ static int lpc3180_address(struct nand_device_s *device, u8 address) { lpc3180_nand_controller_t *lpc3180_info = device->controller_priv; target_t *target = lpc3180_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) { LOG_ERROR("BUG: no LPC3180 NAND flash controller selected"); @@ -406,7 +406,7 @@ static int lpc3180_address(struct nand_device_s *device, u8 address) /* SLC_ADDR = address */ target_write_u32(target, 0x20020004, address); } - + return ERROR_OK; } @@ -414,13 +414,13 @@ static int lpc3180_write_data(struct nand_device_s *device, u16 data) { lpc3180_nand_controller_t *lpc3180_info = device->controller_priv; target_t *target = lpc3180_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) { LOG_ERROR("BUG: no LPC3180 NAND flash controller selected"); @@ -436,7 +436,7 @@ static int lpc3180_write_data(struct nand_device_s *device, u16 data) /* SLC_DATA = data */ target_write_u32(target, 0x20020000, data); } - + return ERROR_OK; } @@ -444,13 +444,13 @@ static int lpc3180_read_data(struct nand_device_s *device, void *data) { lpc3180_nand_controller_t *lpc3180_info = device->controller_priv; target_t *target = lpc3180_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) { LOG_ERROR("BUG: no LPC3180 NAND flash controller selected"); @@ -481,7 +481,7 @@ static int lpc3180_read_data(struct nand_device_s *device, void *data) /* data = SLC_DATA, must use 32-bit access */ target_read_u32(target, 0x20020000, &data32); - + if (device->bus_width == 8) { u8 *data8 = data; @@ -497,8 +497,8 @@ static int lpc3180_read_data(struct nand_device_s *device, void *data) LOG_ERROR("BUG: bus_width neither 8 nor 16 bit"); return ERROR_NAND_OPERATION_FAILED; } - } - + } + return ERROR_OK; } @@ -508,13 +508,13 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, target_t *target = lpc3180_info->target; int retval; u8 status; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) { LOG_ERROR("BUG: no LPC3180 NAND flash controller selected"); @@ -525,30 +525,30 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u8 *page_buffer; u8 *oob_buffer; int quarter, num_quarters; - + if (!data && oob) { LOG_ERROR("LPC3180 MLC controller can't write OOB data only"); return ERROR_NAND_OPERATION_NOT_SUPPORTED; } - + if (oob && (oob_size > 6)) { LOG_ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data"); return ERROR_NAND_OPERATION_NOT_SUPPORTED; } - + if (data_size > (u32)device->page_size) { LOG_ERROR("data size exceeds page size"); return ERROR_NAND_OPERATION_NOT_SUPPORTED; } - + /* MLC_CMD = sequential input */ target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN); page_buffer = malloc(512); - oob_buffer = malloc(6); + oob_buffer = malloc(6); if (device->page_size == 512) { @@ -558,7 +558,7 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, /* MLC_ADDR = row */ target_write_u32(target, 0x200b8004, page & 0xff); target_write_u32(target, 0x200b8004, (page >> 8) & 0xff); - + if (device->address_cycles == 4) target_write_u32(target, 0x200b8004, (page >> 16) & 0xff); } @@ -572,17 +572,17 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, target_write_u32(target, 0x200b8004, page & 0xff); target_write_u32(target, 0x200b8004, (page >> 8) & 0xff); } - + /* when using the MLC controller, we have to treat a large page device * as being made out of four quarters, each the size of a small page device */ num_quarters = (device->page_size == 2048) ? 4 : 1; - + for (quarter = 0; quarter < num_quarters; quarter++) { int thisrun_data_size = (data_size > 512) ? 512 : data_size; int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size; - + memset(page_buffer, 0xff, 512); if (data) { @@ -590,7 +590,7 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, data_size -= thisrun_data_size; data += thisrun_data_size; } - + memset(oob_buffer, 0xff, (device->page_size == 512) ? 6 : 24); if (oob) { @@ -598,38 +598,38 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, oob_size -= thisrun_oob_size; oob += thisrun_oob_size; } - + /* write MLC_ECC_ENC_REG to start encode cycle */ target_write_u32(target, 0x200b8008, 0x0); - + target->type->write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512)); target->type->write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6)); - + /* write MLC_ECC_AUTO_ENC_REG to start auto encode */ target_write_u32(target, 0x200b8010, 0x0); - + if (!lpc3180_controller_ready(device, 1000)) { LOG_ERROR("timeout while waiting for completion of auto encode cycle"); return ERROR_NAND_OPERATION_FAILED; } } - + /* MLC_CMD = auto program command */ target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG); - + if ((retval = nand_read_status(device, &status)) != ERROR_OK) { LOG_ERROR("couldn't read status"); return ERROR_NAND_OPERATION_FAILED; } - + if (status & NAND_STATUS_FAIL) { LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status); return ERROR_NAND_OPERATION_FAILED; } - + free(page_buffer); free(oob_buffer); } @@ -637,7 +637,7 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, { return nand_write_page_raw(device, page, data, data_size, oob, oob_size); } - + return ERROR_OK; } @@ -645,13 +645,13 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u { lpc3180_nand_controller_t *lpc3180_info = device->controller_priv; target_t *target = lpc3180_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) { LOG_ERROR("BUG: no LPC3180 NAND flash controller selected"); @@ -672,13 +672,13 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u return ERROR_NAND_OPERATION_NOT_SUPPORTED; } #endif - + if (data_size > (u32)device->page_size) { LOG_ERROR("data size exceeds page size"); return ERROR_NAND_OPERATION_NOT_SUPPORTED; } - + if (device->page_size == 2048) { page_buffer = malloc(2048); @@ -689,10 +689,10 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u page_buffer = malloc(512); oob_buffer = malloc(16); } - + if (!data && oob) { - /* MLC_CMD = Read OOB + /* MLC_CMD = Read OOB * we can use the READOOB command on both small and large page devices, * as the controller translates the 0x50 command to a 0x0 with appropriate * positioning of the serial buffer read pointer @@ -704,7 +704,7 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u /* MLC_CMD = Read0 */ target_write_u32(target, 0x200b8000, NAND_CMD_READ0); } - + if (device->page_size == 512) { /* small page device */ @@ -714,7 +714,7 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u /* MLC_ADDR = row */ target_write_u32(target, 0x200b8004, page & 0xff); target_write_u32(target, 0x200b8004, (page >> 8) & 0xff); - + if (device->address_cycles == 4) target_write_u32(target, 0x200b8004, (page >> 16) & 0xff); } @@ -728,24 +728,24 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u /* MLC_ADDR = row */ target_write_u32(target, 0x200b8004, page & 0xff); target_write_u32(target, 0x200b8004, (page >> 8) & 0xff); - + /* MLC_CMD = Read Start */ target_write_u32(target, 0x200b8000, NAND_CMD_READSTART); } - + while (page_bytes_done < (u32)device->page_size) { /* MLC_ECC_AUTO_DEC_REG = dummy */ target_write_u32(target, 0x200b8014, 0xaa55aa55); - + if (!lpc3180_controller_ready(device, 1000)) { LOG_ERROR("timeout while waiting for completion of auto decode cycle"); return ERROR_NAND_OPERATION_FAILED; } - + target_read_u32(target, 0x200b8048, &mlc_isr); - + if (mlc_isr & 0x8) { if (mlc_isr & 0x40) @@ -753,15 +753,15 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u LOG_ERROR("uncorrectable error detected: 0x%2.2x", mlc_isr); return ERROR_NAND_OPERATION_FAILED; } - + LOG_WARNING("%i symbol error detected and corrected", ((mlc_isr & 0x30) >> 4) + 1); } - + if (data) { target->type->read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done); } - + if (oob) { target->type->read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done); @@ -770,13 +770,13 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u page_bytes_done += 512; oob_bytes_done += 16; } - + if (data) memcpy(data, page_buffer, data_size); - + if (oob) memcpy(oob, oob_buffer, oob_size); - + free(page_buffer); free(oob_buffer); } @@ -784,7 +784,7 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u { return nand_read_page_raw(device, page, data, data_size, oob, oob_size); } - + return ERROR_OK; } @@ -793,20 +793,20 @@ static int lpc3180_controller_ready(struct nand_device_s *device, int timeout) lpc3180_nand_controller_t *lpc3180_info = device->controller_priv; target_t *target = lpc3180_info->target; u8 status = 0x0; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + do { if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) { /* Read MLC_ISR, wait for controller to become ready */ target_read_u8(target, 0x200b8048, &status); - + if (status & 2) return 1; } @@ -818,7 +818,7 @@ static int lpc3180_controller_ready(struct nand_device_s *device, int timeout) alive_sleep(1); } while (timeout-- > 0); - + return 0; } @@ -826,65 +826,65 @@ static int lpc3180_nand_ready(struct nand_device_s *device, int timeout) { lpc3180_nand_controller_t *lpc3180_info = device->controller_priv; target_t *target = lpc3180_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + do { if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) - { + { u8 status = 0x0; - + /* Read MLC_ISR, wait for NAND flash device to become ready */ target_read_u8(target, 0x200b8048, &status); - + if (status & 1) return 1; } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) { u32 status = 0x0; - + /* Read SLC_STAT and check READY bit */ target_read_u32(target, 0x20020018, &status); - + if (status & 1) return 1; } - + alive_sleep(1); } while (timeout-- > 0); - - return 0; + + return 0; } static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { nand_device_t *device = NULL; lpc3180_nand_controller_t *lpc3180_info = NULL; - char *selected[] = + char *selected[] = { "no", "mlc", "slc" }; - + if ((argc < 1) || (argc > 2)) { return ERROR_COMMAND_SYNTAX_ERROR; } - + device = get_nand_device_by_num(strtoul(args[0], NULL, 0)); if (!device) { command_print(cmd_ctx, "nand device '#%s' is out of bounds", args[0]); return ERROR_OK; } - + lpc3180_info = device->controller_priv; - + if (argc == 2) { if (strcmp(args[1], "mlc") == 0) @@ -900,8 +900,8 @@ static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char return ERROR_COMMAND_SYNTAX_ERROR; } } - + command_print(cmd_ctx, "%s controller selected", selected[lpc3180_info->selected_controller]); - + return ERROR_OK; } diff --git a/src/flash/nand.c b/src/flash/nand.c index 057feb7d..87eb976a 100644 --- a/src/flash/nand.c +++ b/src/flash/nand.c @@ -216,17 +216,17 @@ static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *c { int i; int retval; - + if (argc < 1) { LOG_WARNING("incomplete flash device nand configuration"); return ERROR_FLASH_BANK_INVALID; } - + for (i = 0; nand_flash_controllers[i]; i++) { nand_device_t *p, *c; - + if (strcmp(args[0], nand_flash_controllers[i]->name) == 0) { /* register flash specific commands */ @@ -235,7 +235,7 @@ static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *c LOG_ERROR("couldn't register '%s' commands", args[0]); return retval; } - + c = malloc(sizeof(nand_device_t)); c->controller = nand_flash_controllers[i]; @@ -254,7 +254,7 @@ static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *c free(c); return ERROR_OK; } - + /* put NAND device in linked list */ if (nand_devices) { @@ -267,7 +267,7 @@ static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *c { nand_devices = c; } - + return ERROR_OK; } } @@ -281,16 +281,16 @@ static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *c { LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name); } - + return ERROR_OK; } int nand_register_commands(struct command_context_s *cmd_ctx) { nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands"); - + register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL); - + return ERROR_OK; } @@ -317,7 +317,7 @@ int nand_init(struct command_context_s *cmd_ctx) register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC, "raw access to NAND flash device <num> ['enable'|'disable']"); } - + return ERROR_OK; } @@ -333,7 +333,7 @@ nand_device_t *get_nand_device_by_num(int num) return p; } } - + return NULL; } @@ -342,17 +342,17 @@ static int nand_build_bbt(struct nand_device_s *device, int first, int last) u32 page = 0x0; int i; u8 oob[6]; - + if ((first < 0) || (first >= device->num_blocks)) first = 0; - + if ((last >= device->num_blocks) || (last == -1)) last = device->num_blocks - 1; - + for (i = first; i < last; i++) { nand_read_page(device, page, NULL, 0, oob, 6); - + if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff)) || (((device->page_size == 512) && (oob[5] != 0xff)) || ((device->page_size == 2048) && (oob[0] != 0xff)))) @@ -364,10 +364,10 @@ static int nand_build_bbt(struct nand_device_s *device, int first, int last) { device->blocks[i].is_bad = 0; } - + page += (device->erase_size / device->page_size); } - + return ERROR_OK; } @@ -375,12 +375,12 @@ int nand_read_status(struct nand_device_s *device, u8 *status) { if (!device->device) return ERROR_NAND_DEVICE_NOT_PROBED; - + /* Send read status command */ device->controller->command(device, NAND_CMD_STATUS); - + alive_sleep(1); - + /* read status */ if (device->device->options & NAND_BUSWIDTH_16) { @@ -392,7 +392,7 @@ int nand_read_status(struct nand_device_s *device, u8 *status) { device->controller->read_data(device, status); } - + return ERROR_OK; } @@ -427,13 +427,13 @@ int nand_probe(struct nand_device_s *device) /* clear device data */ device->device = NULL; device->manufacturer = NULL; - + /* clear device parameters */ device->bus_width = 0; device->address_cycles = 0; device->page_size = 0; device->erase_size = 0; - + /* initialize controller (device parameters are zero, use controller default) */ if ((retval = device->controller->init(device) != ERROR_OK)) { @@ -450,13 +450,13 @@ int nand_probe(struct nand_device_s *device) return ERROR_NAND_OPERATION_FAILED; } } - + device->controller->command(device, NAND_CMD_RESET); device->controller->reset(device); device->controller->command(device, NAND_CMD_READID); device->controller->address(device, 0x0); - + if (device->bus_width == 8) { device->controller->read_data(device, &manufacturer_id); @@ -470,7 +470,7 @@ int nand_probe(struct nand_device_s *device) device->controller->read_data(device, &data_buf); device_id = data_buf & 0xff; } - + for (i = 0; nand_flash_ids[i].name; i++) { if (nand_flash_ids[i].id == device_id) @@ -479,7 +479,7 @@ int nand_probe(struct nand_device_s *device) break; } } - + for (i = 0; nand_manuf_ids[i].name; i++) { if (nand_manuf_ids[i].id == manufacturer_id) @@ -488,25 +488,25 @@ int nand_probe(struct nand_device_s *device) break; } } - + if (!device->manufacturer) { device->manufacturer = &nand_manuf_ids[0]; device->manufacturer->id = manufacturer_id; } - + if (!device->device) { LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x", manufacturer_id, device_id); return ERROR_NAND_OPERATION_FAILED; } - + LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name); - + /* initialize device parameters */ - - /* bus width */ + + /* bus width */ if (device->device->options & NAND_BUSWIDTH_16) device->bus_width = 16; else @@ -536,7 +536,7 @@ int nand_probe(struct nand_device_s *device) id_buff[5] = data_buf >> 8; } } - + /* page size */ if (device->device->page_size == 0) { @@ -551,7 +551,7 @@ int nand_probe(struct nand_device_s *device) { device->page_size = device->device->page_size; } - + /* number of address cycles */ if (device->page_size <= 512) { @@ -579,7 +579,7 @@ int nand_probe(struct nand_device_s *device) device->address_cycles = 6; } } - + /* erase size */ if (device->device->erase_size == 0) { @@ -602,7 +602,7 @@ int nand_probe(struct nand_device_s *device) { device->erase_size = device->device->erase_size; } - + /* initialize controller, but leave parameters at the controllers default */ if ((retval = device->controller->init(device) != ERROR_OK)) { @@ -620,10 +620,10 @@ int nand_probe(struct nand_device_s *device) return ERROR_NAND_OPERATION_FAILED; } } - + device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024); device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks); - + for (i = 0; i < device->num_blocks; i++) { device->blocks[i].size = device->erase_size; @@ -631,7 +631,7 @@ int nand_probe(struct nand_device_s *device) device->blocks[i].is_erased = -1; device->blocks[i].is_bad = -1; } - + return ERROR_OK; } @@ -641,13 +641,13 @@ int nand_erase(struct nand_device_s *device, int first_block, int last_block) u32 page; u8 status; int retval; - + if (!device->device) return ERROR_NAND_DEVICE_NOT_PROBED; - + if ((first_block < 0) || (last_block > device->num_blocks)) return ERROR_INVALID_ARGUMENTS; - + /* make sure we know if a block is bad before erasing it */ for (i = first_block; i <= last_block; i++) { @@ -657,25 +657,25 @@ int nand_erase(struct nand_device_s *device, int first_block, int last_block) break; } } - + for (i = first_block; i <= last_block; i++) { /* Send erase setup command */ device->controller->command(device, NAND_CMD_ERASE1); - + page = i * (device->erase_size / device->page_size); - + /* Send page address */ if (device->page_size <= 512) { /* row */ device->controller->address(device, page & 0xff); device->controller->address(device, (page >> 8) & 0xff); - + /* 3rd cycle only on devices with more than 32 MiB */ if (device->address_cycles >= 4) device->controller->address(device, (page >> 16) & 0xff); - + /* 4th cycle only on devices with more than 8 GiB */ if (device->address_cycles >= 5) device->controller->address(device, (page >> 24) & 0xff); @@ -685,12 +685,12 @@ int nand_erase(struct nand_device_s *device, int first_block, int last_block) /* row */ device->controller->address(device, page & 0xff); device->controller->address(device, (page >> 8) & 0xff); - + /* 3rd cycle only on devices with more than 128 MiB */ if (device->address_cycles >= 5) device->controller->address(device, (page >> 16) & 0xff); } - + /* Send erase confirm command */ device->controller->command(device, NAND_CMD_ERASE2); @@ -701,13 +701,13 @@ int nand_erase(struct nand_device_s *device, int first_block, int last_block) LOG_ERROR("timeout waiting for NAND flash block erase to complete"); return ERROR_NAND_OPERATION_TIMEOUT; } - + if ((retval = nand_read_status(device, &status)) != ERROR_OK) { LOG_ERROR("couldn't read status"); return ERROR_NAND_OPERATION_FAILED; } - + if (status & 0x1) { LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status); @@ -716,7 +716,7 @@ int nand_erase(struct nand_device_s *device, int first_block, int last_block) device->blocks[i].is_erased = 1; } - + return ERROR_OK; } @@ -724,74 +724,74 @@ int nand_erase(struct nand_device_s *device, int first_block, int last_block) static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size) { u8 *page; - + if (!device->device) return ERROR_NAND_DEVICE_NOT_PROBED; - + if (address % device->page_size) { LOG_ERROR("reads need to be page aligned"); return ERROR_NAND_OPERATION_FAILED; } - + page = malloc(device->page_size); - + while (data_size > 0 ) { u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size; u32 page_address; - - + + page_address = address / device->page_size; - + nand_read_page(device, page_address, page, device->page_size, NULL, 0); memcpy(data, page, thisrun_size); - + address += thisrun_size; data += thisrun_size; data_size -= thisrun_size; } - + free(page); - + return ERROR_OK; } static int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size) { u8 *page; - + if (!device->device) return ERROR_NAND_DEVICE_NOT_PROBED; - + if (address % device->page_size) { LOG_ERROR("writes need to be page aligned"); return ERROR_NAND_OPERATION_FAILED; } - + page = malloc(device->page_size); - + while (data_size > 0 ) { u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size; u32 page_address; - + memset(page, 0xff, device->page_size); memcpy(page, data, thisrun_size); - + page_address = address / device->page_size; - + nand_write_page(device, page_address, page, device->page_size, NULL, 0); - + address += thisrun_size; data += thisrun_size; data_size -= thisrun_size; } - + free(page); - + return ERROR_OK; } #endif @@ -802,7 +802,7 @@ int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_s if (!device->device) return ERROR_NAND_DEVICE_NOT_PROBED; - + block = page / (device->erase_size / device->page_size); if (device->blocks[block].is_erased == 1) device->blocks[block].is_erased = 0; @@ -817,7 +817,7 @@ static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 { if (!device->device) return ERROR_NAND_DEVICE_NOT_PROBED; - + if (device->use_raw || device->controller->read_page == NULL) return nand_read_page_raw(device, page, data, data_size, oob, oob_size); else @@ -827,7 +827,7 @@ static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size) { u32 i; - + if (!device->device) return ERROR_NAND_DEVICE_NOT_PROBED; @@ -838,14 +838,14 @@ int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 dat device->controller->command(device, NAND_CMD_READ0); else device->controller->command(device, NAND_CMD_READOOB); - + /* column (always 0, we start at the beginning of a page/OOB area) */ device->controller->address(device, 0x0); - + /* row */ device->controller->address(device, page & 0xff); device->controller->address(device, (page >> 8) & 0xff); - + /* 4th cycle only on devices with more than 32 MiB */ if (device->address_cycles >= 4) device->controller->address(device, (page >> 16) & 0xff); @@ -858,7 +858,7 @@ int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 dat { /* large page device */ device->controller->command(device, NAND_CMD_READ0); - + /* column (0 when we start at the beginning of a page, * or 2048 for the beginning of OOB area) */ @@ -867,7 +867,7 @@ int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 dat device->controller->address(device, 0x0); else device->controller->address(device, 0x8); - + /* row */ device->controller->address(device, page & 0xff); device->controller->address(device, (page >> 8) & 0xff); @@ -879,14 +879,14 @@ int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 dat /* large page devices need a start command */ device->controller->command(device, NAND_CMD_READSTART); } - + if (device->controller->nand_ready) { if (!device->controller->nand_ready(device, 100)) return ERROR_NAND_OPERATION_TIMEOUT; } else { alive_sleep(1); } - + if (data) { if (device->controller->read_block_data != NULL) @@ -910,7 +910,7 @@ int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 dat } } } - + if (oob) { if (device->controller->read_block_data != NULL) @@ -934,8 +934,8 @@ int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 dat } } } - - return ERROR_OK; + + return ERROR_OK; } int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size) @@ -943,21 +943,21 @@ int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 da u32 i; int retval; u8 status; - + if (!device->device) return ERROR_NAND_DEVICE_NOT_PROBED; device->controller->command(device, NAND_CMD_SEQIN); - + if (device->page_size <= 512) { /* column (always 0, we start at the beginning of a page/OOB area) */ device->controller->address(device, 0x0); - + /* row */ device->controller->address(device, page & 0xff); device->controller->address(device, (page >> 8) & 0xff); - + /* 4th cycle only on devices with more than 32 MiB */ if (device->address_cycles >= 4) device->controller->address(device, (page >> 16) & 0xff); @@ -976,7 +976,7 @@ int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 da device->controller->address(device, 0x0); else device->controller->address(device, 0x8); - + /* row */ device->controller->address(device, page & 0xff); device->controller->address(device, (page >> 8) & 0xff); @@ -985,7 +985,7 @@ int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 da if (device->address_cycles >= 5) device->controller->address(device, (page >> 16) & 0xff); } - + if (data) { if (device->controller->write_block_data != NULL) @@ -1010,7 +1010,7 @@ int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 da } } } - + if (oob) { if (device->controller->write_block_data != NULL) @@ -1035,41 +1035,41 @@ int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 da } } } - + device->controller->command(device, NAND_CMD_PAGEPROG); - + retval = device->controller->nand_ready ? device->controller->nand_ready(device, 100) : nand_poll_ready(device, 100); if (!retval) return ERROR_NAND_OPERATION_TIMEOUT; - + if ((retval = nand_read_status(device, &status)) != ERROR_OK) { LOG_ERROR("couldn't read status"); return ERROR_NAND_OPERATION_FAILED; } - + if (status & NAND_STATUS_FAIL) { LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status); return ERROR_NAND_OPERATION_FAILED; } - - return ERROR_OK; + + return ERROR_OK; } int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { nand_device_t *p; int i = 0; - + if (!nand_devices) { command_print(cmd_ctx, "no NAND flash devices configured"); return ERROR_OK; } - + for (p = nand_devices; p; p = p->next) { if (p->device) @@ -1078,7 +1078,7 @@ int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char else command_print(cmd_ctx, "#%i: not probed"); } - + return ERROR_OK; } @@ -1089,13 +1089,13 @@ static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd int j = 0; int first = -1; int last = -1; - + if ((argc < 1) || (argc > 3)) { return ERROR_COMMAND_SYNTAX_ERROR; } - + if (argc == 2) { first = last = strtoul(args[1], NULL, 0); @@ -1105,7 +1105,7 @@ static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd first = strtoul(args[1], NULL, 0); last = strtoul(args[2], NULL, 0); } - + p = get_nand_device_by_num(strtoul(args[0], NULL, 0)); if (p) { @@ -1113,24 +1113,24 @@ static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd { if (first >= p->num_blocks) first = p->num_blocks - 1; - + if (last >= p->num_blocks) last = p->num_blocks - 1; - + command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i", i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size); - + for (j = first; j <= last; j++) { char *erase_state, *bad_state; - + if (p->blocks[j].is_erased == 0) erase_state = "not erased"; else if (p->blocks[j].is_erased == 1) erase_state = "erased"; else erase_state = "erase state unknown"; - + if (p->blocks[j].is_bad == 0) bad_state = ""; else if (p->blocks[j].is_bad == 1) @@ -1148,7 +1148,7 @@ static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd command_print(cmd_ctx, "#%i: not probed"); } } - + return ERROR_OK; } @@ -1156,12 +1156,12 @@ static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cm { nand_device_t *p; int retval; - + if (argc != 1) { return ERROR_COMMAND_SYNTAX_ERROR; } - + p = get_nand_device_by_num(strtoul(args[0], NULL, 0)); if (p) { @@ -1182,7 +1182,7 @@ static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cm { command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]); } - + return ERROR_OK; } @@ -1190,19 +1190,19 @@ static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cm { nand_device_t *p; int retval; - + if (argc != 3) { return ERROR_COMMAND_SYNTAX_ERROR; } - + p = get_nand_device_by_num(strtoul(args[0], NULL, 0)); if (p) { int first = strtoul(args[1], NULL, 0); int last = strtoul(args[2], NULL, 0); - + if ((retval = nand_erase(p, first, last)) == ERROR_OK) { command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name); @@ -1220,7 +1220,7 @@ static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cm { command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]); } - + return ERROR_OK; } @@ -1230,19 +1230,19 @@ int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char int retval; int first = -1; int last = -1; - + if ((argc < 1) || (argc > 3) || (argc == 2)) { return ERROR_COMMAND_SYNTAX_ERROR; } - + if (argc == 3) { first = strtoul(args[1], NULL, 0); last = strtoul(args[2], NULL, 0); } - + p = get_nand_device_by_num(strtoul(args[0], NULL, 0)); if (p) { @@ -1263,20 +1263,20 @@ int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char { command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]); } - + return ERROR_OK; } static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { nand_device_t *p; - + if (argc != 4) { return ERROR_COMMAND_SYNTAX_ERROR; } - + p = get_nand_device_by_num(strtoul(args[0], NULL, 0)); if (p) { @@ -1286,7 +1286,7 @@ static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd { command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]); } - + return ERROR_OK; } @@ -1296,20 +1296,20 @@ static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cm u32 binary_size; u32 buf_cnt; enum oob_formats oob_format = NAND_OOB_NONE; - + fileio_t fileio; - + duration_t duration; char *duration_text; - + nand_device_t *p; - + if (argc < 3) { return ERROR_COMMAND_SYNTAX_ERROR; } - + p = get_nand_device_by_num(strtoul(args[0], NULL, 0)); if (p) { @@ -1318,9 +1318,9 @@ static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cm u8 *oob = NULL; u32 oob_size = 0; const int *eccpos = NULL; - + offset = strtoul(args[2], NULL, 0); - + if (argc > 3) { int i; @@ -1341,16 +1341,16 @@ static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cm } } } - + duration_start_measure(&duration); if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK) { return ERROR_OK; } - + buf_cnt = binary_size = fileio.size; - + if (!(oob_format & NAND_OOB_ONLY)) { page_size = p->page_size; @@ -1368,7 +1368,7 @@ static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cm } oob = malloc(oob_size); } - + if (offset % p->page_size) { command_print(cmd_ctx, "only page size aligned offsets and sizes are supported"); @@ -1377,11 +1377,11 @@ static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cm free(page); return ERROR_OK; } - + while (buf_cnt > 0) { u32 size_read; - + if (NULL != page) { fileio_read(&fileio, page_size, page, &size_read); @@ -1428,7 +1428,7 @@ static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cm memset(oob + size_read, 0xff, oob_size - size_read); } } - + if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK) { command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x", @@ -1458,19 +1458,19 @@ static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cm { command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]); } - + return ERROR_OK; } static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { nand_device_t *p; - + if (argc < 4) { return ERROR_COMMAND_SYNTAX_ERROR; } - + p = get_nand_device_by_num(strtoul(args[0], NULL, 0)); if (p) { @@ -1480,7 +1480,7 @@ static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd duration_t duration; char *duration_text; int retval; - + u8 *page = NULL; u32 page_size = 0; u8 *oob = NULL; @@ -1489,7 +1489,7 @@ static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd u32 size = strtoul(args[3], NULL, 0); u32 bytes_done = 0; enum oob_formats oob_format = NAND_OOB_NONE; - + if (argc > 4) { int i; @@ -1500,16 +1500,16 @@ static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd else if (!strcmp(args[i], "oob_only")) oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY; else - command_print(cmd_ctx, "unknown option: '%s'", args[i]); + command_print(cmd_ctx, "unknown option: '%s'", args[i]); } } - + if ((address % p->page_size) || (size % p->page_size)) { command_print(cmd_ctx, "only page size aligned addresses and sizes are supported"); return ERROR_OK; } - + if (!(oob_format & NAND_OOB_ONLY)) { page_size = p->page_size; @@ -1524,14 +1524,14 @@ static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd oob_size = 64; oob = malloc(oob_size); } - + if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK) { return ERROR_OK; } - + duration_start_measure(&duration); - + while (size > 0) { u32 size_written; @@ -1539,27 +1539,27 @@ static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd { command_print(cmd_ctx, "reading NAND flash page failed"); free(page); - free(oob); + free(oob); fileio_close(&fileio); return ERROR_OK; } - + if (NULL != page) { fileio_write(&fileio, page_size, page, &size_written); bytes_done += page_size; } - + if (NULL != oob) { fileio_write(&fileio, oob_size, oob, &size_written); bytes_done += oob_size; } - + size -= p->page_size; address += p->page_size; } - + free(page); page = NULL; free(oob); @@ -1580,19 +1580,19 @@ static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd { command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]); } - + return ERROR_OK; } static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { nand_device_t *p; - + if ((argc < 1) || (argc > 2)) { return ERROR_COMMAND_SYNTAX_ERROR; } - + p = get_nand_device_by_num(strtoul(args[0], NULL, 0)); if (p) { @@ -1613,7 +1613,7 @@ static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, cha return ERROR_COMMAND_SYNTAX_ERROR; } } - + command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled"); } else @@ -1625,6 +1625,6 @@ static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, cha { command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]); } - + return ERROR_OK; } diff --git a/src/flash/nand.h b/src/flash/nand.h index b3c6b6b5..6f3ea272 100644 --- a/src/flash/nand.h +++ b/src/flash/nand.h @@ -99,7 +99,7 @@ enum typedef struct nand_manufacturer_s { - int id; + int id; char *name; } nand_manufacturer_t; @@ -115,43 +115,43 @@ typedef struct nand_info_s /* Option constants for bizarre disfunctionality and real features */ -enum { +enum { /* Chip can not auto increment pages */ NAND_NO_AUTOINCR = 0x00000001, - + /* Buswitdh is 16 bit */ NAND_BUSWIDTH_16 = 0x00000002, - + /* Device supports partial programming without padding */ NAND_NO_PADDING = 0x00000004, - + /* Chip has cache program function */ NAND_CACHEPRG = 0x00000008, - + /* Chip has copy back function */ NAND_COPYBACK = 0x00000010, - + /* AND Chip which has 4 banks and a confusing page / block * assignment. See Renesas datasheet for further information */ NAND_IS_AND = 0x00000020, - + /* Chip has a array of 4 pages which can be read without * additional ready /busy waits */ NAND_4PAGE_ARRAY = 0x00000040, - + /* Chip requires that BBT is periodically rewritten to prevent * bits from adjacent blocks from 'leaking' in altering data. * This happens with the Renesas AG-AND chips, possibly others. */ BBT_AUTO_REFRESH = 0x00000080, - + /* Chip does not require ready check on read. True * for all large page devices, as they do not support * autoincrement.*/ NAND_NO_READRDY = 0x00000100, - + /* Options valid for Samsung large page devices */ NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK), - + /* Options for new chips with large page size. The pagesize and the * erasesize is determined from the extended id bytes */ @@ -175,7 +175,7 @@ enum NAND_CMD_READID = 0x90, NAND_CMD_ERASE2 = 0xd0, NAND_CMD_RESET = 0xff, - + /* Extended commands for large page devices */ NAND_CMD_READSTART = 0x30, NAND_CMD_RNDOUTSTART = 0xE0, @@ -198,7 +198,7 @@ enum oob_formats NAND_OOB_NONE = 0x0, /* no OOB data at all */ NAND_OOB_RAW = 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */ NAND_OOB_ONLY = 0x2, /* only OOB data */ - NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */ + NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */ NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */ NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */ NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */ diff --git a/src/flash/s3c2410_nand.c b/src/flash/s3c2410_nand.c index 951677c5..7a642ee7 100644 --- a/src/flash/s3c2410_nand.c +++ b/src/flash/s3c2410_nand.c @@ -59,7 +59,7 @@ static int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char * struct nand_device_s *device) { s3c24xx_nand_controller_t *info; - + info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device); if (info == NULL) { return ERROR_NAND_DEVICE_INVALID; @@ -70,7 +70,7 @@ static int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char * info->addr = S3C2410_NFADDR; info->data = S3C2410_NFDATA; info->nfstat = S3C2410_NFSTAT; - + return ERROR_OK; } @@ -79,7 +79,7 @@ static int s3c2410_init(struct nand_device_s *device) s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; target_t *target = s3c24xx_info->target; - target_write_u32(target, S3C2410_NFCONF, + target_write_u32(target, S3C2410_NFCONF, S3C2410_NFCONF_EN | S3C2410_NFCONF_TACLS(3) | S3C2410_NFCONF_TWRPH0(5) | S3C2410_NFCONF_TWRPH1(3)); @@ -95,7 +95,7 @@ static int s3c2410_write_data(struct nand_device_s *device, u16 data) LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + target_write_u32(target, S3C2410_NFDATA, data); return ERROR_OK; } @@ -104,13 +104,13 @@ static int s3c2410_read_data(struct nand_device_s *device, void *data) { s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; target_t *target = s3c24xx_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - target_read_u8(target, S3C2410_NFDATA, data); + target_read_u8(target, S3C2410_NFDATA, data); return ERROR_OK; } @@ -124,14 +124,14 @@ static int s3c2410_nand_ready(struct nand_device_s *device, int timeout) LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + do { target_read_u8(target, S3C2410_NFSTAT, &status); - + if (status & S3C2410_NFSTAT_BUSY) return 1; - alive_sleep(1); + alive_sleep(1); } while (timeout-- > 0); return 0; diff --git a/src/flash/s3c2412_nand.c b/src/flash/s3c2412_nand.c index 271b3c40..a7b13719 100644 --- a/src/flash/s3c2412_nand.c +++ b/src/flash/s3c2412_nand.c @@ -69,7 +69,7 @@ static int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char * info->addr = S3C2440_NFADDR; info->data = S3C2440_NFDATA; info->nfstat = S3C2412_NFSTAT; - + return ERROR_OK; } diff --git a/src/flash/s3c2440_nand.c b/src/flash/s3c2440_nand.c index 61aace65..85a50989 100644 --- a/src/flash/s3c2440_nand.c +++ b/src/flash/s3c2440_nand.c @@ -59,7 +59,7 @@ static int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char * struct nand_device_s *device) { s3c24xx_nand_controller_t *info; - + info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device); if (info == NULL) { return ERROR_NAND_DEVICE_INVALID; @@ -70,7 +70,7 @@ static int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char * info->addr = S3C2440_NFADDR; info->data = S3C2440_NFDATA; info->nfstat = S3C2440_NFSTAT; - + return ERROR_OK; } @@ -100,10 +100,10 @@ int s3c2440_nand_ready(struct nand_device_s *device, int timeout) LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - - do { + + do { target_read_u8(target, s3c24xx_info->nfstat, &status); - + if (status & S3C2440_NFSTAT_READY) return 1; @@ -130,7 +130,7 @@ int s3c2440_read_block_data(struct nand_device_s *device, u8 *data, int data_siz return ERROR_NAND_OPERATION_FAILED; } - while (data_size >= 4) { + while (data_size >= 4) { target_read_u32(target, nfdata, &tmp); data[0] = tmp; @@ -164,7 +164,7 @@ int s3c2440_write_block_data(struct nand_device_s *device, u8 *data, int data_si return ERROR_NAND_OPERATION_FAILED; } - while (data_size >= 4) { + while (data_size >= 4) { tmp = le_to_h_u32(data); target_write_u32(target, nfdata, tmp); diff --git a/src/flash/s3c2443_nand.c b/src/flash/s3c2443_nand.c index 7dc3aa3a..a50689d5 100644 --- a/src/flash/s3c2443_nand.c +++ b/src/flash/s3c2443_nand.c @@ -58,7 +58,7 @@ static int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char * struct nand_device_s *device) { s3c24xx_nand_controller_t *info; - + info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device); if (info == NULL) { return ERROR_NAND_DEVICE_INVALID; @@ -69,7 +69,7 @@ static int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char * info->addr = S3C2440_NFADDR; info->data = S3C2440_NFDATA; info->nfstat = S3C2412_NFSTAT; - + return ERROR_OK; } diff --git a/src/flash/s3c24xx_nand.c b/src/flash/s3c24xx_nand.c index ecd48eea..291b658c 100644 --- a/src/flash/s3c24xx_nand.c +++ b/src/flash/s3c24xx_nand.c @@ -37,7 +37,7 @@ s3c24xx_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, struct nand_device_s *device) { s3c24xx_nand_controller_t *s3c24xx_info; - + s3c24xx_info = malloc(sizeof(s3c24xx_nand_controller_t)); if (s3c24xx_info == NULL) { LOG_ERROR("no memory for nand controller\n"); @@ -69,9 +69,9 @@ int s3c24xx_reset(struct nand_device_s *device) LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + target_write_u32(target, s3c24xx_info->cmd, 0xff); - + return ERROR_OK; } @@ -79,7 +79,7 @@ int s3c24xx_command(struct nand_device_s *device, u8 command) { s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; target_t *target = s3c24xx_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; @@ -94,12 +94,12 @@ int s3c24xx_address(struct nand_device_s *device, u8 address) { s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; target_t *target = s3c24xx_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + target_write_u16(target, s3c24xx_info->addr, address); return ERROR_OK; } @@ -113,7 +113,7 @@ int s3c24xx_write_data(struct nand_device_s *device, u16 data) LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - + target_write_u8(target, s3c24xx_info->data, data); return ERROR_OK; } @@ -122,7 +122,7 @@ int s3c24xx_read_data(struct nand_device_s *device, void *data) { s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; target_t *target = s3c24xx_info->target; - + if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; diff --git a/src/flash/s3c24xx_nand.h b/src/flash/s3c24xx_nand.h index 8f96f2d2..99e4cf0a 100644 --- a/src/flash/s3c24xx_nand.h +++ b/src/flash/s3c24xx_nand.h @@ -30,12 +30,12 @@ typedef struct s3c24xx_nand_controller_s { struct target_s *target; - + /* register addresses */ u32 cmd; u32 addr; u32 data; - u32 nfstat; + u32 nfstat; } s3c24xx_nand_controller_t; /* Default to using the un-translated NAND register based address */ diff --git a/src/flash/stellaris.h b/src/flash/stellaris.h index 317309a6..3694feb3 100644 --- a/src/flash/stellaris.h +++ b/src/flash/stellaris.h @@ -47,7 +47,6 @@ typedef struct stellaris_flash_bank_s u32 rcc; u8 mck_valid; u32 mck_freq; - } stellaris_flash_bank_t; /* STELLARIS control registers */ @@ -66,7 +65,7 @@ typedef struct stellaris_flash_bank_s #define FMPRE 0x130 #define FMPPE 0x134 -#define USECRL 0x140 +#define USECRL 0x140 #define FLASH_CONTROL_BASE 0x400FD000 #define FLASH_FMA (FLASH_CONTROL_BASE|0x000) @@ -87,7 +86,7 @@ typedef struct stellaris_flash_bank_s #define FMC_COMT (1<<3) #define FMC_MERASE (1<<2) #define FMC_ERASE (1<<1) -#define FMC_WRITE (1<<0) +#define FMC_WRITE (1<<0) /* STELLARIS constants */ diff --git a/src/flash/stm32x.h b/src/flash/stm32x.h index 587f97f7..864141bd 100644 --- a/src/flash/stm32x.h +++ b/src/flash/stm32x.h @@ -66,17 +66,17 @@ typedef struct stm32x_flash_bank_s #define FLASH_PG (1<<0) #define FLASH_PER (1<<1) -#define FLASH_MER (1<<2) +#define FLASH_MER (1<<2) #define FLASH_OPTPG (1<<4) #define FLASH_OPTER (1<<5) #define FLASH_STRT (1<<6) #define FLASH_LOCK (1<<7) #define FLASH_OPTWRE (1<<9) -/* FLASH_SR regsiter bits */ +/* FLASH_SR register bits */ #define FLASH_BSY (1<<0) -#define FLASH_PGERR (1<<2) +#define FLASH_PGERR (1<<2) #define FLASH_WRPRTERR (1<<4) #define FLASH_EOP (1<<5) diff --git a/src/flash/str7x.h b/src/flash/str7x.h index 5d0b1824..7e904fa2 100644 --- a/src/flash/str7x.h +++ b/src/flash/str7x.h @@ -59,14 +59,14 @@ enum str7x_status_codes #define FLASH_AR 0x00000010 #define FLASH_ER 0x00000014 #define FLASH_NVWPAR 0x0000DFB0 -#define FLASH_NVAPR0 0x0000DFB8 -#define FLASH_NVAPR1 0x0000DFBC +#define FLASH_NVAPR0 0x0000DFB8 +#define FLASH_NVAPR1 0x0000DFBC /* FLASH_CR0 register bits */ #define FLASH_WMS 0x80000000 #define FLASH_SUSP 0x40000000 -#define FLASH_WPG 0x20000000 +#define FLASH_WPG 0x20000000 #define FLASH_DWPG 0x10000000 #define FLASH_SER 0x08000000 #define FLASH_SPR 0x01000000 @@ -76,7 +76,7 @@ enum str7x_status_codes #define FLASH_BSYA1 0x00000004 #define FLASH_BSYA0 0x00000002 -/* FLASH_CR1 regsiter bits */ +/* FLASH_CR1 register bits */ #define FLASH_B1S 0x02000000 #define FLASH_B0S 0x01000000 |