diff options
Diffstat (limited to 'src/target/event')
| -rw-r--r-- | src/target/event/sam7s256_reset.script | 18 | ||||
| -rw-r--r-- | src/target/event/sam7x256_reset.script | 18 | ||||
| -rw-r--r-- | src/target/event/str912_reset.script | 5 |
3 files changed, 24 insertions, 17 deletions
diff --git a/src/target/event/sam7s256_reset.script b/src/target/event/sam7s256_reset.script index 456341d6..1d389287 100644 --- a/src/target/event/sam7s256_reset.script +++ b/src/target/event/sam7s256_reset.script @@ -5,13 +5,19 @@ # # http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html # -mww 0xfffffd44 0x00008000 # disable watchdog -mww 0xfffffd08 0xa5000001 # enable user reset -mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator +# disable watchdog +mww 0xfffffd44 0x00008000 +# enable user reset +mww 0xfffffd08 0xa5000001 +# CKGR_MOR : enable the main oscillator +mww 0xfffffc20 0x00000601 sleep 10 -mww 0xfffffc2c 0x00481c0e # CKGR_PLLR: 96.1097 MHz +# CKGR_PLLR: 96.1097 MHz +mww 0xfffffc2c 0x00481c0e sleep 10 -mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz +# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz +mww 0xfffffc30 0x00000007 sleep 10 -mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60) +# MC_FMR: flash mode (FWS=1,FMCN=60) +mww 0xffffff60 0x003c0100 sleep 100 diff --git a/src/target/event/sam7x256_reset.script b/src/target/event/sam7x256_reset.script index 456341d6..1612366c 100644 --- a/src/target/event/sam7x256_reset.script +++ b/src/target/event/sam7x256_reset.script @@ -5,13 +5,19 @@ # # http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html # -mww 0xfffffd44 0x00008000 # disable watchdog -mww 0xfffffd08 0xa5000001 # enable user reset -mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator +# disable watchdog +mww 0xfffffd44 0x00008000 +# enable user reset +mww 0xfffffd08 0xa5000001 +# CKGR_MOR : enable the main oscillator +mww 0xfffffc20 0x00000601 sleep 10 -mww 0xfffffc2c 0x00481c0e # CKGR_PLLR: 96.1097 MHz +# CKGR_PLLR: 96.1097 MHz +mww 0xfffffc2c 0x00481c0e sleep 10 -mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz +# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz +mww 0xfffffc30 0x00000007 sleep 10 -mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60) +# MC_FMR: flash mode (FWS=1,FMCN=60) +mww 0xffffff60 0x003c0100 sleep 100 diff --git a/src/target/event/str912_reset.script b/src/target/event/str912_reset.script deleted file mode 100644 index 33c62047..00000000 --- a/src/target/event/str912_reset.script +++ /dev/null @@ -1,5 +0,0 @@ -# -- Enable 96K RAM */ -mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled - -str9x flash_config 0 4 2 0 0x80000 -flash protect 0 0 7 off |