6 files changed, 37 insertions, 39 deletions

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 11f6d9cc..9e131d8b 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -995,6 +995,13 @@ int arm11_assert_reset(struct target_s *target)
     arm11->trst_active = true;
 #endif
 
+    if (target->reset_halt)
+    {
+    	int retval;
+		if ((retval = target_halt(target))!=ERROR_OK)
+			return retval;
+    }
+
     return ERROR_OK;
 }
 
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 117e9cb1..547bf3c4 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -815,6 +815,12 @@ int arm7_9_assert_reset(target_t *target)
 
 	armv4_5_invalidate_core_regs(target);
 
+    if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
+	{
+		/* debug entry was already prepared in arm7_9_assert_reset() */
+		target->debug_reason = DBG_REASON_DBGRQ;
+	}
+	
 	return ERROR_OK;
 
 }
@@ -832,13 +838,6 @@ int arm7_9_deassert_reset(target_t *target)
 		/* set up embedded ice registers again */
 		if ((retval=target->type->examine(target))!=ERROR_OK)
 			return retval;
-		
-		if (target->reset_halt)
-		{
-			/* halt the CPU as embedded ice was not set up in reset */
-			if ((retval=target->type->halt(target))!=ERROR_OK)
-				return retval;
-		}
 	}
 	return retval;
 }
@@ -975,9 +974,9 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 
 int arm7_9_halt(target_t *target)
 {
-	if ((target->state==TARGET_RESET)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0))
+	if (target->state==TARGET_RESET)
 	{
-		LOG_WARNING("arm7/9 can't halt a target in reset if srst pulls trst - halting after reset");
+		LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
 		return ERROR_OK;
 	}
 
@@ -998,24 +997,6 @@ int arm7_9_halt(target_t *target)
 		LOG_WARNING("target was in unknown state when halt was requested");
 	}
 
-	if (target->state == TARGET_RESET)
-	{
-		if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
-		{
-			LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
-			return ERROR_TARGET_FAILURE;
-		}
-		else
-		{
-			/* we came here in a reset_halt or reset_init sequence
-			 * debug entry was already prepared in arm7_9_assert_reset()
-			 */
-			target->debug_reason = DBG_REASON_DBGRQ;
-
-			return ERROR_OK;
-		}
-	}
-
 	if (arm7_9->use_dbgrq)
 	{
 		/* program EmbeddedICE Debug Control Register to assert DBGRQ
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index e305c018..255fcd03 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -762,6 +762,13 @@ int cortex_m3_assert_reset(target_t *target)
 	
 	armv7m_invalidate_core_regs(target);
 
+    if (target->reset_halt)
+    {
+    	int retval;
+		if ((retval = target_halt(target))!=ERROR_OK)
+			return retval;
+    }
+	
 	return ERROR_OK;
 }
 
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index e89ee844..2a34bd0b 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -266,6 +266,14 @@ int mips_m4k_assert_reset(target_t *target)
 
 	mips32_invalidate_core_regs(target);
 
+    if (target->reset_halt)
+    {
+    	int retval;
+		if ((retval = target_halt(target))!=ERROR_OK)
+			return retval;
+    }
+	
+	
 	return ERROR_OK;
 }
 
diff --git a/src/target/target.c b/src/target/target.c
index 5bd16622..0950e436 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -308,18 +308,6 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo
 		target = target->next;
 	}
 
-	/* request target halt if necessary, and schedule further action */
-	target = targets;
-	while (target)
-	{
-		if (reset_mode!=RESET_RUN)
-		{
-			if ((retval = target_halt(target))!=ERROR_OK)
-				return retval;
-		}
-		target = target->next;
-	}
-
 	target = targets;
 	while (target)
 	{
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 3e957a56..0c99abf7 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1579,6 +1579,13 @@ int xscale_assert_reset(target_t *target)
 	jtag_execute_queue();
 
 	target->state = TARGET_RESET;
+	
+    if (target->reset_halt)
+    {
+    	int retval;
+		if ((retval = target_halt(target))!=ERROR_OK)
+			return retval;
+    }
 
 	return ERROR_OK;
 }