3 files changed, 22 insertions, 10 deletions
diff --git a/src/target/event/str912_program.script b/src/target/event/str912_program.script
deleted file mode 100644
index df0239b9..00000000
--- a/src/target/event/str912_program.script
+++ /dev/null
@@ -1,9 +0,0 @@
-str9x flash_config 0 4 2 0 0x80000
-flash protect 0 0 7 off
-
-
-
-
-
-
-
diff --git a/src/target/event/str912_reset.script b/src/target/event/str912_reset.script
new file mode 100644
index 00000000..8178c82c
--- /dev/null
+++ b/src/target/event/str912_reset.script
@@ -0,0 +1,21 @@
+mww 0xFFFFFD44, 0x00008000 #Disable watchdog
+mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator
+sleep 20
+mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR
+sleep 20
+
+
+# -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
+#    when the bank 0 is the boot bank, then enable the Bank 1. */
+
+mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB
+mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB
+mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0
+mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000
+mww 0x54000018, 0x18 #Enable CS on both banks
+
+# -- Enable 96K RAM */
+mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled
+arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register
+
+flash protect 0 0 7 off
diff --git a/src/target/target/str912.cfg b/src/target/target/str912.cfg
index 71aa062d..c749cd2c 100644
--- a/src/target/target/str912.cfg
+++ b/src/target/target/str912.cfg
@@ -15,7 +15,7 @@ jtag_device 5 0x1 0x1 0x1e
 target arm966e little reset_halt 1 arm966e
 run_and_halt_time 0 30
 
-target_script 0 gdb_program_config event/str912_program.script
+target_script 0 reset event/str912_reset.script
 
 working_area 0 0x50000000 16384 nobackup