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-rw-r--r--src/target/dsp5680xx.c10
-rw-r--r--src/target/dsp5680xx.h6
2 files changed, 8 insertions, 8 deletions
diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c
index 3db31d30..f3f25a17 100644
--- a/src/target/dsp5680xx.c
+++ b/src/target/dsp5680xx.c
@@ -726,11 +726,11 @@ static int dsp5680xx_read(struct target * target, uint32_t address, unsigned siz
err_check_propagate(retval);
context.flush = 0;
}
-
+
context.flush = 1;
retval = dsp5680xx_execute_queue();
err_check_propagate(retval);
-
+
return retval;
}
@@ -913,7 +913,7 @@ static int dsp5680xx_read_buffer(struct target * target, uint32_t address, uint3
return ERROR_OK;
}
// read_buffer is called when the verify_image command is executed.
- // The "/2" solves the byte/word addressing issue.
+ // The "/2" solves the byte/word addressing issue.
return dsp5680xx_read(target,address,2,size/2,buffer);
}
@@ -1120,14 +1120,14 @@ int dsp5680xx_f_erase_check(struct target * target, uint8_t * erased,uint32_t se
*erased = (uint8_t)(hfm_ustat&HFM_USTAT_MASK_BLANK);
return retval;
}
-
+
static int erase_sector(struct target * target, int sector, uint16_t * hfm_ustat){
int retval;
retval = dsp5680xx_f_execute_command(target,HFM_PAGE_ERASE,HFM_FLASH_BASE_ADDR+sector*HFM_SECTOR_SIZE/2,0,hfm_ustat,1);
err_check_propagate(retval);
return retval;
}
-
+
static int mass_erase(struct target * target, uint16_t * hfm_ustat){
int retval;
retval = dsp5680xx_f_execute_command(target,HFM_MASS_ERASE,0,0,hfm_ustat,1);
diff --git a/src/target/dsp5680xx.h b/src/target/dsp5680xx.h
index da494c9a..50ab9907 100644
--- a/src/target/dsp5680xx.h
+++ b/src/target/dsp5680xx.h
@@ -114,13 +114,13 @@
#define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */
#define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */
#define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */
-#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
+#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
#define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */
#define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */
#define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
#define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */
#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */
-#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
+#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
//----------------------------------------------------------------
@@ -179,7 +179,7 @@
//----------------------------------------------------------------
#define MC568013_EONCE_OBASE_ADDR 0xFF
// The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...)
-#define MC568013_EONCE_TX_RX_ADDR 0xFFFE //
+#define MC568013_EONCE_TX_RX_ADDR 0xFFFE //
#define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF // Relative to EONCE_OBASE_ADDR
#define MC568013_EONCE_OCR 0xFFA0 // Relative to EONCE_OBASE_ADDR
//----------------------------------------------------------------