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-rw-r--r--src/target/cortex_a8.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 7a705153..e73994e9 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1253,6 +1253,24 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
exit(-1);
}
+ /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
+ /* invalidate I-Cache */
+ if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+ {
+ /* Invalidate ICache single entry with MVA, repeat this for all cache
+ lines in the address range, Cortex-A8 has fixed 64 byte line length */
+ /* Invalidate Cache single entry with MVA to PoU */
+ for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+ armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
+ }
+ /* invalidate D-Cache */
+ if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
+ {
+ /* Invalidate Cache single entry with MVA to PoC */
+ for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+ armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
+ }
+
return retval;
}