diff options
Diffstat (limited to 'tcl/board')
| -rw-r--r-- | tcl/board/embedded-artists_lpc2478-32.cfg | 148 |
1 files changed, 148 insertions, 0 deletions
diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg new file mode 100644 index 00000000..49396990 --- /dev/null +++ b/tcl/board/embedded-artists_lpc2478-32.cfg @@ -0,0 +1,148 @@ +# Embedded Artists eval board for LPC2478 +# http://www.embeddedartists.com/ + +# Delays on reset lines +adapter_nsrst_delay 500 +jtag_ntrst_delay 1 + +# Adaptive JTAG clocking through RTCK. +# +jtag_rclk 20 + +# Target device: LPC2478 +set CCLK 72000 +source [find target/lpc2478.cfg] + +# A working area will help speeding the flash programming +$_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0 + +# External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB) +flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe + +# Helper +# +proc read_register {register} { + set result "" + mem2array result 32 $register 1 + return $result(0) +} + + +# Enable the PLL. +# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator. +# Note: The PLL output runs at a frequency N times the desired CPU clock. +# It in unavoidable that the CPU clock drops down to (4 MHz/N) during +# the initialization! +# Here: N=4 +# Note that if the PLL is already active at the time this script is +# called, the effective value of N is the value of CCLKCFG at that time! +# +proc enable_pll {} { + # Disconnect PLL in case it is already connected + if {[expr [read_register 0xE01FC080] & 0x03] == 3} { + # Disconnect it, but leave it enabled + # (This MUST be done in two steps) + mww 0xE01FC080 0x00000001 # PLLCON: disconnect PLL + mww 0xE01FC08C 0x000000AA # PLLFEED + mww 0xE01FC08C 0x00000055 # PLLFEED + } + # Disable PLL (as it might already be enabled at this time!) + mww 0xE01FC080 0x00000000 # PLLCON: disable PLL + mww 0xE01FC08C 0x000000AA # PLLFEED + mww 0xE01FC08C 0x00000055 # PLLFEED + + # Setup PLL to generate 288 MHz from internal RC oscillator + mww 0xE01FC10C 0x00000000 # CLKSRCSEL: IRC + mww 0xE01FC084 0x00000023 # PLLCFG: N=1, M=36 + mww 0xE01FC08C 0x000000AA # PLLFEED + mww 0xE01FC08C 0x00000055 # PLLFEED + mww 0xE01FC080 0x00000001 # PLLCON: enable PLL + mww 0xE01FC08C 0x000000AA # PLLFEED + mww 0xE01FC08C 0x00000055 # PLLFEED + sleep 100 + mww 0xE01FC104 0x00000003 # CCLKCFG: divide by 4 (72 MHz) + mww 0xE01FC080 0x00000003 # PLLCON: connect PLL + mww 0xE01FC08C 0x000000AA # PLLFEED + mww 0xE01FC08C 0x00000055 # PLLFEED +} + + +# Event handlers +# +$_TARGETNAME configure -event reset-start { + # Back to the slow JTAG clock + jtag_rclk 20 +} + + +$_TARGETNAME configure -event reset-init { + + arm core_state arm + arm7_9 dcc_downloads enable # Speed up downloads by using DCC transfer + arm7_9 fast_memory_access enable + + # Peripheral clocks + mww 0xE01FC0C4 0x04280FFE # PCONP: (reset value) + + # Map the user flash to the vector table area (0x00...0x3F) + mww 0xE01FC040 0x00000001 # MEMMAP: User flash + + # Memory accelerator module + mww 0xE01FC004 0x00000003 # MAMTIM: 3 clock cycles + mww 0xE01FC000 0x00000002 # MAMCR: fully enabled + + # Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0) + mww 0xE002C014 0x55010115 # PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0, + # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0, + # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3 + mww 0xE002C018 0x55555555 # PINSEL6: P3.0...P3.15=D0...D15 + mww 0xE002C01C 0x55555555 # PINSEL7: P3.16...P3.31=D16...D31 + mww 0xE002C020 0x55555555 # PINSEL8: P4.0...P4.15=A0...A15 + mww 0xE002C024 0x50051555 # PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE, + # P4.25=WE, P4.30=CS0, P4.31=CS1 + mww 0xFFE08000 0x00000001 # EMCControl: Enable EMC + + # Start PLL, then use faster JTAG clock + enable_pll + jtag_rclk 3000 + + # 16-bit flash @ CS0 (SST39VF3201-70) + mww 0xFFE08200 0x00080081 # EMCStaticConfig0: 16 bit, PB=1, buffers on + mww 0xFFE08204 0x00000000 # EMCStaticWaitWen0 + mww 0xFFE08208 0x00000000 # EMCStaticWaitOen0 + mww 0xFFE0820C 0x00000005 # EMCStaticWaitRd0 + mww 0xFFE08210 0x00000005 # EMCStaticWaitPage0 + mww 0xFFE08214 0x00000003 # EMCStaticWaitWr0 + mww 0xFFE08218 0x00000001 # EMCStaticWaitTurn0 + + # 8-bit NAND @ CS1 + # TODO + + # 32-bit SDRAM @ DYCS0 (K4M563233G-HN75) + mww 0xFFE08028 0x00000001 # EMCDynamicReadConfig + mww 0xFFE08030 0x00000001 # EMCDynamicRP + mww 0xFFE08034 0x00000003 # EMCDynamicRAS + mww 0xFFE08038 0x00000005 # EMCDynamicSREX + mww 0xFFE0803C 0x00000001 # EMCDynamicAPR + mww 0xFFE08040 0x00000005 # EMCDynamicDAL + mww 0xFFE08044 0x00000001 # EMCDynamicWR + mww 0xFFE08048 0x00000005 # EMCDynamicRC + mww 0xFFE0804C 0x00000005 # EMCDynamicRFC + mww 0xFFE08050 0x00000005 # EMCDynamicXSR + mww 0xFFE08054 0x00000001 # EMCDynamicRRD + mww 0xFFE08058 0x00000001 # EMCDynamicMRD + # + mww 0xFFE08104 0x00000202 # EMCDynamicRasCas0 + mww 0xFFE08100 0x00005488 # EMCDynamicConfig0 + sleep 100 + mww 0xFFE08020 0x00000183 # EMCDynamicControl: Clock on continuously, NOP + sleep 10 + mww 0xFFE08020 0x00000103 # EMCDynamicControl: PRECHARGE-ALL + mww 0xFFE08024 0x00000046 # EMCDynamicRefresh + sleep 100 + mww 0xFFE08020 0x00000083 # EMCDynamicControl: MODE + mdw 0xA0011000 1 # Set SDRAM mode register + mww 0xFFE08020 0x00000000 # EMCDynamicControl: NORMAL + mww 0xFFE08100 0x00085488 # EMCDynamicConfig0: Enable buffers +} + |