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-rw-r--r--tcl/target/hilscher_netx50.cfg50
1 files changed, 50 insertions, 0 deletions
diff --git a/tcl/target/hilscher_netx50.cfg b/tcl/target/hilscher_netx50.cfg
new file mode 100644
index 00000000..1129544e
--- /dev/null
+++ b/tcl/target/hilscher_netx50.cfg
@@ -0,0 +1,50 @@
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+#Hilscher netX 50 CPU
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME netx50
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966021
+}
+
+# jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# that TAP is associated with a target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# On netX50 SDRAM is not accessible at offset 0xDEAD0-0xDEADF as it is busy from
+# DMA controller at init. This function will setup a dummy DMA to free this ares
+# and must be called before using SDRAM
+proc sdram_fix { } {
+
+ mww 0x1c005830 0x00000001
+
+ mww 0x1c005104 0xBFFFFFFC
+ mww 0x1c00510c 0x00480001
+ mww 0x1c005110 0x00000001
+
+ sleep 100
+
+ mww 0x1c00510c 0
+ mww 0x1c005110 0
+ mww 0x1c005830 0x00000000
+
+ puts "SDRAM Fix executed!"
+}