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-rw-r--r--tcl/target/omap3530.cfg57
1 files changed, 57 insertions, 0 deletions
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
new file mode 100644
index 00000000..ad8f8ea8
--- /dev/null
+++ b/tcl/target/omap3530.cfg
@@ -0,0 +1,57 @@
+#File omap3530.cfg - as found on the BEAGLEBOARD
+# Assumption is it is generic for all OMAP3530
+
+#TI OMAP3 processor - http://www.ti.com
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME omap3
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a little endianness
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0x0B6D602F
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID -disable
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x0b7ae02f
+
+target create omap3.cpu cortex_m3 -endian little -chain-position omap3.cpu
+
+jtag configure $_CHIPNAME.cpu -event tap-enable {
+ puts "Enabling Cortex-A8 @ OMAP3"
+ irscan omap3.jrc 7 -endstate IRPAUSE
+ drscan omap3.jrc 8 0x89 -endstate DRPAUSE
+ irscan omap3.jrc 2 -endstate IRPAUSE
+ drscan omap3.jrc 32 0xa3002108 -endstate RUN/IDLE
+ irscan omap3.jrc 0x3F -endstate RUN/IDLE
+ runtest 10
+ puts "Cortex-A8 @ OMAP3 enabled"
+}
+
+proc omap3_dbginit { } {
+ version
+ jtag tapenable omap3.cpu
+ targets
+ # sleep 1000
+ # dap apsel 1
+ # sleep 1000
+ # dap apsel 1
+ # dap info 1
+ omap3.cpu mww 0x54011FB0 0xC5ACCE55 4
+ omap3.cpu mdw 0x54011314
+ omap3.cpu mdw 0x54011314
+ # omap3.cpu mdw 0x54011080
+ omap3.cpu mww 0x5401d030 0x00002000 4
+}