diff options
Diffstat (limited to 'tcl/target/pxa255.cfg')
| -rw-r--r-- | tcl/target/pxa255.cfg | 94 |
1 files changed, 8 insertions, 86 deletions
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg index c79ea4c9..93d27bd3 100644 --- a/tcl/target/pxa255.cfg +++ b/tcl/target/pxa255.cfg @@ -1,3 +1,6 @@ +# PXA255 chip ... originally from Intel, PXA line was sold to Marvell. +# This chip is now at end-of-life. Final orders have been taken. + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { @@ -13,92 +16,11 @@ if { [info exists ENDIAN] } { if { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID } else { - # force an error till we get a good number - set _CPUTAPID 0xffffffff -} - -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID - -jtag_nsrst_delay 200 -jtag_ntrst_delay 200 -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa255 -$_TARGETNAME configure -event reset-init { - xscale cp15 15 0x00002001 #Enable CP0 and CP13 access - # - # setup GPIO - # - mww 0x40E00018 0x00008000 #CPSR0 - sleep 20 - mww 0x40E0001C 0x00000002 #GPSR1 - sleep 20 - mww 0x40E00020 0x00000008 #GPSR2 - sleep 20 - mww 0x40E0000C 0x00008000 #GPDR0 - sleep 20 - mww 0x40E00054 0x80000000 #GAFR0_L - sleep 20 - mww 0x40E00058 0x00188010 #GAFR0_H - sleep 20 - mww 0x40E0005C 0x60908018 #GAFR1_L - sleep 20 - mww 0x40E0000C 0x0280E000 #GPDR0 - sleep 20 - mww 0x40E00010 0x821C88B2 #GPDR1 - sleep 20 - mww 0x40E00014 0x000F03DB #GPDR2 - sleep 20 - mww 0x40E00000 0x000F03DB #GPLR0 - sleep 20 - - - mww 0x40F00004 0x00000020 #PSSR - sleep 20 - - # - # setup memory controller - # - mww 0x48000008 0x01111998 #MSC0 - sleep 20 - mww 0x48000010 0x00047ff0 #MSC2 - sleep 20 - mww 0x48000014 0x00000000 #MECR - sleep 20 - mww 0x48000028 0x00010504 #MCMEM0 - sleep 20 - mww 0x4800002C 0x00010504 #MCMEM1 - sleep 20 - mww 0x48000030 0x00010504 #MCATT0 - sleep 20 - mww 0x48000034 0x00010504 #MCATT1 - sleep 20 - mww 0x48000038 0x00004715 #MCIO0 - sleep 20 - mww 0x4800003C 0x00004715 #MCIO1 - sleep 20 - # - mww 0x48000004 0x03CA4018 #MDREF - sleep 20 - mww 0x48000004 0x004B4018 #MDREF - sleep 20 - mww 0x48000004 0x000B4018 #MDREF - sleep 20 - mww 0x48000004 0x000BC018 #MDREF - sleep 20 - mww 0x48000000 0x00001AC8 #MDCNFG - sleep 20 - - sleep 20 - - mww 0x48000000 0x00001AC9 #MDCNFG - sleep 20 - mww 0x48000040 0x00000000 #MDMRS - sleep 20 + set _CPUTAPID 0x69264013 } -reset_config trst_and_srst - - - -#xscale debug_handler 0 0xFFFF0800 # debug handler base address +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e -irmask 0x1f -expected-id $_CPUTAPID +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME +debug_level 3 |