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-rw-r--r--tcl/target/stm32.cfg8
-rw-r--r--tcl/target/stm32xl.cfg6
2 files changed, 12 insertions, 2 deletions
diff --git a/tcl/target/stm32.cfg b/tcl/target/stm32.cfg
index 86e6ebb8..eef12699 100644
--- a/tcl/target/stm32.cfg
+++ b/tcl/target/stm32.cfg
@@ -52,18 +52,22 @@ if { [info exists BSTAPID ] } {
set _BSTAPID4 0x06414041
# Connectivity line devices, Rev A and Rev Z
set _BSTAPID5 0x06418041
+ # XL line devices, Rev A
+ set _BSTAPID6 0x06430041
}
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
- -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
+ -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
+ -expected-id $_BSTAPID6
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32x 0x08000000 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/stm32xl.cfg b/tcl/target/stm32xl.cfg
new file mode 100644
index 00000000..cde07df2
--- /dev/null
+++ b/tcl/target/stm32xl.cfg
@@ -0,0 +1,6 @@
+# script for stm32xl family (dual flash bank)
+source [find target/stm32.cfg]
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME stm32x 0x08080000 0 0 0 $_TARGETNAME