diff options
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/board/csb732.cfg | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg new file mode 100644 index 00000000..8bf77cb3 --- /dev/null +++ b/tcl/board/csb732.cfg @@ -0,0 +1,71 @@ +# The Cogent CSB732 board has a single i.MX35 chip +source [find target/imx35.cfg] + +# Determined by trial and error +reset_config trst_and_srst combined +jtag_nsrst_delay 200 +jtag_ntrst_delay 200 + +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { csb732_init } + +# Bare-bones initialization of core clocks and SDRAM +proc csb732_init { } { + + # Disable fast writing only for init + memwrite burst disable + + # All delay loops are omitted. + # We assume the interpreter latency is enough. + + # Allow access to all coprocessors + arm11 mcr imx35.cpu 15 0 15 1 0 0x2001 + + # Disable MMU, caches, write buffer + arm11 mcr imx35.cpu 15 0 1 0 0 0x78 + + # Grant manager access to all domains + arm11 mcr imx35.cpu 15 0 3 0 0 0xFFFFFFFF + + # Set ARM clock to 532 MHz, AHB to 133 MHz + mww 0x53F80004 0x1000 + + # Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz + mww 0x53F8001C 0xB2C01 + + set ESDMISC 0xB8001010 + set ESDCFG0 0xB8001004 + set ESDCTL0 0xB8001000 + + # Enable DDR + mww $ESDMISC 0x4 + + # Timing + mww $ESDCFG0 0x007fff3f + + # CS0 + mww $ESDCTL0 0x92120080 + + # Precharge all dummy write + mww 0x80000400 0 + + # Enable CS) auto-refresh + mww $ESDCTL0 0xA2120080 + + # Refresh twice (dummy writes) + mww 0x80000000 0 + mww 0x80000000 0 + + # Enable CS0 load mode register + mww $ESDCTL0 0xB2120080 + + # Dummy writes + mwb 0x80000033 0x01 + mwb 0x81000000 0x01 + + mww $ESDCTL0 0x82226080 + mww 0x80000000 0 + + # Re-enable fast writing + memwrite burst enable +} |