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-rw-r--r--tcl/target/ti_dm355.cfg6
-rw-r--r--tcl/target/ti_dm365.cfg6
-rw-r--r--tcl/target/ti_dm6446.cfg6
3 files changed, 18 insertions, 0 deletions
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index e5ef8cd2..abfba109 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -86,6 +86,12 @@ $_TARGETNAME configure \
-work-area-size 0x4000 \
-work-area-backup 0
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it. OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index 4f22ea27..06a52d28 100644
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -88,6 +88,12 @@ $_TARGETNAME configure \
-work-area-size 0x4000 \
-work-area-backup 0
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it. OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index 289518b7..cc23ad44 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -68,6 +68,12 @@ set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
+# on the PLL and starts using it. OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable